ICS671-03

3.3 Volt Zero Delay, Low Skew Buffer

MDS 671-03 A

3

Revision 072501

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408) 295-9800 tel • www.icst.com

PRELIMINARY INFORMATION

Parameter

Conditions

Units

ABSOLUTE MAXIMUM RATINGS (note 1)

Supply voltage, VDD

Referenced to GND

-0.5

7

V

Inputs and Clock Outputs

Referenced to GND

-0.5

VDD+0.5

V

CLKIN and FBIN Inputs

-0.5

5.5

Electrostatic Discharge

MIL-STD-883

2000

V

Ambient Operating Temperature

-40

85

°C

Soldering Temperature

Max of 10 seconds

260

°C

Junction temperature

150

°C

Storage temperature

-65

150

°C

DC CHARACTERISTICS (VDD = 3.3 V unless specified otherwise)

DC CHARACTERISTICS (VDD = 3.3 V unless specified otherwise)

DC CHARACTERISTICS (VDD = 3.3 V unless specified otherwise)

Operating Voltage, VDD

3.00

3.60

V

Input High Voltage, VIH

2

V

Input Low Voltage, VIL

0.8

V

Output High Voltage, VOH

IOH=-12 mA

2.4

V

Output Low Voltage, VOL

IOL=12 mA

0.4

V

Output High Voltage, VOH, CMOS level

IOH=-8mA

VDD-0.4

V

Operating Supply Current, IDD (Note 2)

No Load, S2=1, S1=1

70

mA

Power Down Supply Current, IDD

CLKIN=0, S2=0, S1=1

1.3

mA

CLKIN=0 (Note 3)

1.3

mA

Short Circuit Current

Each output

±50

mA

Input Capacitance

S2, S1, FBIN

5

pF

AC CHARACTERISTICS (VDD = 3.3 V unless specified otherwise)

AC CHARACTERISTICS (VDD = 3.3 V unless specified otherwise)

AC CHARACTERISTICS (VDD = 3.3 V unless specified otherwise)

Input Clock Frequency

See table on page 2

10

133

MHz

Output Clock Frequency

See table on page 2

10

133

MHz

Output Clock Rise Time, CL=30pF

0.8 to 2.0V

1.5

ns

Output Clock Fall Time, CL=30pF

2.0 to 0.8V

1.25

ns

Output Clock Duty Cycle, VDD=3.3V

At VDD/2

45

50

55

%

Device to Device Skew, equally loaded

rising edges at VDD/2

700

ps

Output to Output Skew, equally loaded

rising edges at VDD/2

200

ps

Input to Output Skew, FBIN to CLKA4, S1=1, S0 =1

(Note 2)

rising edges at VDD/2

±250

ps

Maximum Absolute Jitter

130

ps

Cycle to Cycle Jitter, 30pF loads

300

ps

PLL Lock Time (Note 4)

1.0

ms

Electrical Specifications

Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the

device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may

affect device reliability.

2. With CLKIN = 100 MHz, FBIN to CLKA4, all outputs at 100 MHz.

3. When there is no clock signal present at CLKIN, the ICS671-03 will enter a power down mode. The PLL is

stopped and the outputs are tri-state.

4. With VDD at a steady state, and valid clocks at CLKIN and FBIN.