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AMD-761 Datasheet(PDF) 39 Page - Advanced Micro Devices

No. de pieza AMD-761
Descripción Electrónicos  AMD-761-TM System Controller Software/BIOS Design Guide
PDF  264 Pages
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Fabricante Electrónico  AMD [Advanced Micro Devices]
Página de inicio  http://www.amd.com
Logo AMD - Advanced Micro Devices

AMD-761 Datasheet(HTML) 39 Page - Advanced Micro Devices

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Chapter 2
AMD-761™ System Controller Programmer’s Interface
27
24081D—February 2002
AMD-761™ System Controller Software/BIOS Design Guide
Preliminary Information
2.4.3
Device 0: PCI Configuration Registers
In Table 6, the column entitled Offset consists of the register
number specified in the Configuration Address register bits
[7:2] concatenated with 0b00 to form a simple 1-byte offset.
Reserved configuration registers return 0 when read.
Table 6.
Device 0, Function 0 Configuration Register Map
Host to PCI Bridge (Device 0, Function 0)
Offset
Reference
Device ID
Vendor ID
0x00–0x03
“Dev0:F0:0x00”
on page 30
Status
Command
0x04–0x07
“Dev0:F0:0x04”
on page 32
Class Code = 0x060000
Revision ID
0x08–0x0B
“Dev0:F0:0x08”
on page 35
Reserved
Header Type
Latency Timer
Reserved
0x0C–0x0F
“Dev0:F0:0x0C”
on page 36
BAR0 - AGP Virtual Address Space
0x10–0x13
“Dev0:F0:0x10”
on page 37
BAR1 - GART Memory-Mapped Control Registers Pointer
0x14–0x17
“Dev0:F0:0x14”
on page 39
Reserved
0x18–0x1B
Reserved
0x1C–0x33
Reserved
Capabilities
Pointer: A0
0x34–0x37
“Dev0:F0:0x34”
on page 41
Reserved
0x38–0x43
Extended BIU Control
0x44–0x53
“Dev0:F0:0x44”
on page 42
ECC Mode/Status
0x48–0x4B
“Dev0:F0:0x48”
on page 44
PCI Control
0x4C–0x4F
“Dev0:F0:0x4C”
on page 47
AMD Athlon™ Processor System Bus Dynamic Compensation
0x50–0x53
“Dev0:F0:0x50”
on page 49
DRAM Timing
0x54–0x57
“Dev0:F0:0x54”
on page 51
DRAM Mode/Status
0x58–0x5B
“Dev0:F0:0x58”
on page 56
Reserved
0x5C–0x5F
BIU0 Status/Control
0x60–0x63
“Dev0:F0:0x60”
on page 61
BIU0 SIP
0x64–0x67
“Dev0:F0:0x64”
on page 64



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