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ADP2165/ADP2166

Data Sheet

Rev. B | Page 14 of 23

APPLICATIONS INFORMATION

ADIsimPOWER DESIGN TOOL

The ADP2165/ADP2166 are supported by the ADIsimPower

design tool set. ADIsimPower is a collection of tools that produce

complete power designs optimized to a specific design goal. The

tools allow the user to generate a full schematic, bill of materials,

and calculate performance in minutes. ADIsimPower can optimize

designs for cost, area, efficiency, and parts count while taking

into consideration the operating conditions and limitations of

the IC and all real external components. The ADIsimPower tool

can be found at www.analog.com/ADIsimPower, and the user

can request an unpopulated board through the tool.

INPUT CAPACITOR SELECTION

The input capacitor reduces the input voltage ripple caused by

the switch current on the PVIN pin. Place the input capacitor as

close as possible to the PVIN pin. A ceramic capacitor in the 10 µF

to 47 µF range is recommended. The loop that is composed of

this input capacitor, the high-side NFET, and the low-side NFET

must be kept as small as possible.

The voltage rating of the input capacitor must be greater than the

maximum input voltage. The rms current rating of the input

capacitor must be larger than the value calculated by the

following equation:

)

(

OUT

CIN_RMS

−

OUTPUT VOLTAGE SETTING

The output voltage of the ADP2165/ADP2166 is set by an

external resistive divider. The resistor values are calculated

using the following equation:

VOUT = 0.6 ×













BOT

TOP

To limit the output voltage accuracy degradation due to FB bias

current (0.1 µA maximum) to less than 0.5% (maximum), ensure

that RBOT < 30 kΩ.

Table 5 lists the recommended resistor divider for various output

voltages.

Table 5. Resistor Divider for Various Output Voltages

VOUT (V)

RTOP ± 1% (kΩ)

RBOT ± 1% (kΩ)

1.0

1.2

1.5

1.8

2.5

47.5

3.3

2.21

VOLTAGE CONVERSION LIMITATIONS

The minimum output voltage for a given input voltage and

switching frequency is constrained by the minimum on time.

The minimum on time of the ADP2165/ADP2166 is typically

100 ns. The minimum output voltage at a given input voltage

and frequency can be calculated using the following equation:

VOUT_MIN = VPVIN × tON_MIN × fSW − (RDSON_HS − RDSON_LS) ×

IOUT_MIN × tON_MIN × fSW − (RDSON_LS + RL) × IOUT_MIN

(1)

where:

VOUT_MIN is the minimum output voltage.

tON_MIN is the minimum on time.

IOUT_MIN is the minimum output current.

fSW is the switching frequency.

RDSON_HS is the high-side MOSFET on resistance.

RDSON_LS is the low-side MOSFET on resistance.

RL is the series resistance of the output inductor.

The maximum output voltage for a given input voltage and

switching frequency is constrained by the minimum off time

and the maximum duty cycle. The minimum off time is typically

100 ns, and the maximum duty cycle of the ADP2165/ADP2166

is typically 90%.

The maximum output voltage, limited by the minimum off time

at a given input voltage and frequency, can be calculated using

the following equation:

VOUT_MAX = VPVIN × (1 − tOFF_MIN × fSW) − (RDSON_HS − RDSON_LS) ×

IOUT_MAX × (1 − tOFF_MIN × fSW) − (RDSON_LS + RL) × IOUT_MAX (2)

where:

VOUT_MAX is the maximum output voltage.

tOFF_MIN is the minimum off time.

IOUT_MAX is the maximum output current.

The maximum output voltage, limited by the maximum duty

cycle at a given input voltage, can be calculated using the

following equation:

VOUT_MAX = DMAX × VPVIN

(3)

where DMAX is the maximum duty cycle.

As Equation 1 to Equation 3 show, reducing the switching

frequency alleviates the minimum on time and minimum off

time limitation.

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