BLF2425M7L250P_2425M7LS250P#5

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Product data sheet

Rev. 5 — 1 September 2015

2 of 11

BLF2425M7L(S)250P

Power LDMOS transistor

2. Pinning information

[1]

Connected to flange.

3. Ordering information

4. Limiting values

Table 2.

Pinning

Pin

Description

Simplified outline

Graphic symbol

BLF2425M7L250P (SOT539A)

1drain1

2drain2

3gate1

4gate2

5source

[1]

BLF2425M7LS250P (SOT539B)

1drain1

2drain2

3gate1

4gate2

5source

[1]

5

12

4

3

4

3

5

1

2

sym117

5

12

4

3

4

3

5

1

2

sym117

Table 3.

Ordering information

Type number

Package

Name

Description

Version

BLF2425M7L250P

-

flanged balanced ceramic package;

2 mounting holes; 4 leads

SOT539A

BLF2425M7LS250P -

earless flanged balanced ceramic package; 4 leads

SOT539B

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

drain-source voltage

-

65

V

gate-source voltage

0.5

+13

V

storage temperature

65

+150

C

junction temperature

-

225

C