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MIC5321 Datasheet(PDF) 9 Page - Microchip Technology

No. de pieza MIC5321
Descripción Electrónicos  High-Performance, Dual 150 mA 關Cap Ultra-Low Dropout Regulator
PDF  26 Pages
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Fabricante Electrónico  MICROCHIP [Microchip Technology]
Página de inicio  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MIC5321 Datasheet(HTML) 9 Page - Microchip Technology

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2022 Microchip Technology Inc. and its subsidiaries
DS20006678A-page 9
MIC5321
4.0
APPLICATION INFORMATION
4.1
Enable/Shutdown
The MIC5321 comes with a single active-high enable
pin that allows both regulators to be disabled
simultaneously. Forcing the enable pin low disables the
regulator and sends it into a “zero” off-mode current
state. In this state, current consumed by the regulator
goes nearly to zero. Forcing the enable pin high
enables the output voltage. The active-high enable pin
uses CMOS technology and the enable pin cannot be
left floating; a floating enable pin may cause an
indeterminate state on the output.
4.2
Input Capacitor
The MIC5321 is a high-performance, high-bandwidth
device. Therefore, it requires a well-bypassed input
supply for optimal performance. A 1 µF capacitor is
required from the input to ground to provide stability.
Low-ESR ceramic capacitors provide optimal
performance at a minimum of space. Additional
high-frequency capacitors, such as small-valued NPO
dielectric-type capacitors, help filter out high-frequency
noise and are good practice in any RF-based circuit.
4.3
Output Capacitor
The MIC5321 requires an output capacitor of 1 µF or
greater to maintain stability. The design is optimized for
use with low-ESR ceramic chip capacitors. High ESR
capacitors may cause high frequency oscillation. The
output capacitor can be increased, but performance
has been optimized for a 1 µF ceramic output capacitor
and does not improve significantly with larger
capacitance.
X7R/X5R dielectric-type ceramic capacitors are
recommended
because
of
their
temperature
performance. X7R-type capacitors change capacitance
by 15% over their operating temperature range and are
the most stable type of ceramic capacitors. Z5U and
Y5V dielectric capacitors change value by as much as
50% and 60%, respectively, over their operating
temperature ranges. To use a ceramic chip capacitor
with Y5V dielectric, the value must be much higher than
an X7R ceramic capacitor to ensure the same
minimum capacitance over the equivalent operating
temperature range.
4.4
Bypass Capacitor
A capacitor can be placed from the noise bypass pin to
ground to reduce output voltage noise. The capacitor
bypasses the internal reference. A 0.1 µF capacitor is
recommended for applications that require low-noise
outputs. The bypass capacitor can be increased,
further reducing noise and improving PSRR. Turn-on
time increases slightly with respect to bypass
capacitance. A unique, quick-start circuit allows the
MIC5321 to drive a large capacitor on the bypass pin
without significantly slowing turn-on time. Refer to the
Typical Performance Curves section for performance
with different bypass capacitors.
4.5
No-Load Stability
Unlike many other voltage regulators, the MIC5321 will
remain stable and in regulation with no load. This is
especially important in CMOS RAM keep-alive
applications.
4.6
Thermal Considerations
The MIC5321 is designed to provide 150 mA of
continuous current for both outputs in a very small
package. Maximum ambient operating temperature
can be calculated based on the output current and the
voltage drop across the part. Given that the input
voltage is 3.3V, the output voltage is 2.8V for VOUT1,
2.5V for VOUT2 and the output current equals 150 mA.
The actual power dissipation of the regulator circuit can
be determined using the equation:
EQUATION 4-1:
Because this device is CMOS and the ground current
is typically <150 µA over the load range, the power
dissipation contributed by the ground current is less
than 1% and can be ignored for this calculation.
EQUATION 4-2:
To determine the maximum ambient operating
temperature
of
the
package,
use
the
junction-to-ambient thermal resistance of the device
and the following basic equation:
EQUATION 4-3:
The table below shows the junction-to-ambient thermal
resistance for the UDFN package option.
Package
θJA Rec. Min.
Footprint
θJC
6-Lead UDFN
100°C/W
2°C/W
PD
VIN VOUT1
IOUT1
VIN VOUT2
+
IOUT2
VIN
+
IGND
=
PD
3.3V 2.8V
150mA
3.3V 1.5V
+
150mA
=
PD
0.345W
=
PD MAX
TJ MAX
TA
JA
-------------------------------
=
Where:
TJ(MAX) = 125°C, the max. junction temp. of the die.
θJA = Thermal resistance of 100°C/W.



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