XIO2000 datasheet(72/150 Pages) TI

72 / 150 page

Classic PCI Configuration Space

November 2005

SCPS097B

4.43 Next Item Pointer Register

The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This

PCI register offset:

81h

Read-only

Default value:

90h

BIT NUMBER

RESET STATE

4.44 Subsystem Vendor ID Register

This register, used for system and option card identification purposes, may be required for certain operating

systems. This read-only register is initialized through the EEPROM and can be written through the subsystem

alias register. This register is reset by a PCI Express reset (PERST), a GRST, or the internally-generated

power-on reset.

PCI register offset:

84h

Read-only

Default value:

0000h

BIT NUMBER

RESET STATE

4.45 Subsystem ID Register

This register, used for system and option card identification purposes, may be required for certain operating

systems. This read-only register is initialized through the EEPROM and can be written through the subsystem

alias register. This register is reset by a PCI Express reset (PERST), a GRST, or the internally-generated

power-on reset.

PCI register offset:

86h

Read-only

Default value:

0000h

BIT NUMBER

RESET STATE

4.46 PCI Express Capability ID Register

This read-only register identifies the linked list item as the register for PCI Express capabilities. The register

returns 10h when read.

PCI register offset:

90h

Read-only

Default value:

10h

BIT NUMBER

RESET STATE

XIO2000 Datasheet(PDF) 72 Page - Texas Instruments

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