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XIO2000 Datasheet(PDF) 133 Page - Texas Instruments

No. de pieza XIO2000
Descripción Electrónicos  XIO2000 PCI Express to PCI Bus Translation Bridge
PDF  150 Pages
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Fabricante Electrónico  TI [Texas Instruments]
Página de inicio  http://www.ti.com
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XIO2000 Datasheet(HTML) 133 Page - Texas Instruments

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Memory-Mapped TI Proprietary Register Space
121
November 2005
SCPS097B
6.24 Serial IRQ Edge Control Register
This register controls the edge mode of each IRQ in the serial IRQ stream. This register is an alias for the serial
IRQ edge control register in the classic PCI configuration space (offset E2h, see Section 4.73). See
Table 6−13 for a complete description of the register contents.
Device control memory window register offset:
4Ah
Register type:
Read/Write
Default value:
0000h
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 6−13. Serial IRQ Edge Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
15†
IRQ15_MODE
RW
IRQ 15 edge mode
0 = Edge mode (default)
1 = Level mode
14†
IRQ14_MODE
RW
IRQ 14 edge mode
0 = Edge mode (default)
1 = Level mode
13†
IRQ13_MODE
RW
IRQ 13 edge mode
0 = Edge mode (default)
1 = Level mode
12†
IRQ12_MODE
RW
IRQ 12 edge mode
0 = Edge mode (default)
1 = Level mode
11†
IRQ11_MODE
RW
IRQ 11 edge mode
0 = Edge mode (default)
1 = Level mode
10†
IRQ10_MODE
RW
IRQ 10 edge mode
0 = Edge mode (default)
1 = Level mode
9†
IRQ9_MODE
RW
IRQ 9 edge mode
0 = Edge mode (default)
1 = Level mode
8†
IRQ8_MODE
RW
IRQ 8 edge mode
0 = Edge mode (default)
1 = Level mode
7†
IRQ7_MODE
RW
IRQ 7 edge mode
0 = Edge mode (default)
1 = Level mode
6†
IRQ6_MODE
RW
IRQ 6 edge mode
0 = Edge mode (default)
1 = Level mode
5†
IRQ5_MODE
RW
IRQ 5 edge mode
0 = Edge mode (default)
1 = Level mode
4†
IRQ4_MODE
RW
IRQ 4 edge mode
0 = Edge mode (default)
1 = Level mode
† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.



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