SCAS641

– JULY 2000

11

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tc

3V48 clock period†

f(3V48)= 48 MHz

15.03

ns

tjit(cc)

Cycle to cycle jitter

f(3V48) = 48 MHz,

f(HCLK) = 100 or 133 MHz,

VDD = 3.3 V, Measured at 1.5 V

350

ps

tdc

Duty cycle

f(3V48) = 48 MHz

45%

55%

tsk(o)

3V48 output skew

3V48x

3V48x

f(3V48) = 48 MHz,

f(HCLK) = 100 or 133 MHz,

VDD = 3.3 V, Measured at 1.5 V

250

ps

t(off)

3V48 clock to PCI

3V48x

PCIx

f(3V48) = 48 MHz,

Measured points at 1.5 V,

Measured at rising edges

1.5

3.5

ns

tr

Rise time

VO = 0.4 V to 2.4 V

1

4

ns

tf

Fall time

VO = 0.4 V to 2.4 V

1

4

ns

† The average over any 1– s period of time is greater than the minimum specified period.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tc

REF clock period†

f(REF)= 14.318 MHz

69.84

ns

tjit(cc)

Cycle to cycle jitter

f(HCLK) = 100 or 133 MHz

1

ps

tdc

Duty cycle

f(REF) = 14.318 MHz

52%

62%

tr

Rise time

VO = 0.4 V to 2.4 V

1

4

ns

tf

Fall time

VO = 0.4 V to 2.4 V

1

4

ns

† The average over any 1– s period of time is greater than the minimum specified period.