Microsemi

Colorado Division

800 Hoyt Street, Broomfield, CO. 80020, 303-469-2161, Fax: 303-466-3775

Page 3

Copyright

2000

2003-02-05 Rev. IR

SRM4010

40A Synchronous Rectifier Module

CO L O RA D O DI V I S I O N

FUNCTIONAL PIN DESCR

FUNCTIONAL PIN DESCR

FUNCTIONAL PIN DESCR

FUNCTIONAL PIN DESCR IPTION

IPTION

IPTION

IPTION

Pin

Number

Pin

Name

Function and description

1

CT CH

This is the power MOSFET drain for the Catch device. It connects to the output inductor and the

positive of the forward converter transformer secondary. This power device carries the load

current when the primary switch is OFF.

2

FWD

This is the power MOSFET Drain for the forward device. This pin connects to the negative of

the forward transformer. This carries the current in the forward direction when the primary

switch is ON.

3

SGND

The signal reference for external tailoring parts.

4

This is the input signal to the linear regulator. It is usually fed from internal diodes from the

Drains of the Catch and forward MOSFETs. In some cases with low voltage outputs, this can be

used as an input if the peak voltage on the MOSFETs is less than what is required to operate the

regulator. The regulator requires 8 volts of input to regulate at 5 volts.

5

5V regulator output. It is also available for use with feedback circuitry that is on the secondary

side. This is useful in low voltage converters where the voltage is too low to operate optical

couplers directly from the output.

6

PGND

This is the common of the power MOSFET synchronous rectifiers

7

CDLY

Pin 7 is used to ensure that the transformer can be reset during light load operation. To allow

reset, the forward drive is inhibited for a time before the turn on of the Catch MOSFET Gate. A

capacitor to ground sets the time duration where the forward MOSFET Gate drive is disabled. A

typical value is 22 pF. Increasing the capacitor increases the hold off time.

8

CP DT

Pin 8 is used for an external capacitor to tailor the prediction time for the Catch synchronous

rectifier. The external capacitor connects between pin 8 and SGND. This time is the time

between the rise of the Catch Drain voltage and the rise of the Catch Gate voltage. Typical

values of this capacitor are 10 to 47 pF. Increasing the capacitance increases the prediction time

delay.

9

SPD

Pin 9 is used to tailor the module’s ability to differentiate between valid turn on of the Catch

diode and ringing that can occur at light load. This pin is normally open, which sets the boundary

for normal turn on at 50nS for the drain voltage to fall from 4.3 volts to 1.7 volts. In the open

case, fall times between the thresholds that are faster than 50nS are interpreted as valid turn

ON’s caused by the primary being switched off. Transitions slower than 50nS are interpreted as

ringing, which occurs in light load discontinuous operation. In the light load case, the Catch

MOSFET is not turned on. The speed of this threshold can be changed by biasing pin 9. If the

controller is not sensing normal turn off from the primary, biasing this pin to ground through a

resistor can make the controller respond to slower transitions. If the controller is responding

falsely to ringing in a discontinuous mode or skip cycle operation, the controller can be made to

reject faster ringing by biasing pin 9 to the +5V regulator output through a resistor.