A Product Line of

Diodes Incorporated

PI2DPX2063

7

July 2022

© 2022 Copyright Diodes Incorporated. All Rights Reserved.

PI2DPX2063

Document Number DS43839 Rev 2-2

www.diodes.com

Table 1. Configuration Table

OP_MODE<3:0>

IN0

IN1

IN2

IN3

AUXP

AUXN

Mode

0000-0001

−

−

−

−

−

−

Reserved

0010

OUT0

(DP0)

OUT1

(DP1)

OUT2

(DP2)

OUT3

(DP3)

−

−

4-lane DP + AUX

0011

OUT0

(DP3)

OUT1

(DP2)

OUT2

(DP1)

OUT3

(DP0)

−

−

4-lane DP + AUX (flipped)

<0100> ~ <1111>

−

−

−

−

−

−

Reserved

Notes: 1) <0010> default at power on.

I/O Termination Resistance under Different Conditions

Symbol

Parameter

Resistance

Units

RX Terminal

Rin-pd

Input res at EN=0

78k to GND

Ω

Rin-Active

Input res at active mode condition

50 to VbiasRx1

Ω

Rin-DP-standby

Input res in DP standby mode

78k to GND

Ω

Rin-DP-active

Input res in DP active mode

50 to VbiasRx1

Ω

Rin-DP-D3

Input res in DP D3 mode

78k to GND

Ω

TX Terminal

Rout-pd

Output res at EN=0

78k to GND

Ω

Rout-Active

Output res at active mode condition

50 to VDD

Ω

Rout-DP-standby

Output res in DP standby mode

78k to GND

Ω

Rout-DP-active

Output res in DP active mode

50 to VDD

Ω

Rout-DP-D3

Output res in DP D3 mode

78k to GND

Ω

DisplayPort Mode

By default, all channels will go to active mode if HPD bit = 1. The ON/OFF of each DP channel is controlled by the Aux lane count.

Operation Mode

ML_TX_x_n

ML_TX_x_p

Source

Connector

Sink

Connector

Sink

Connector

Tx

Rx

50

50

Vbias_Tx

50

50

Vbias_Rx

Upstream device

Downstream device

ML_TX_x_n

ML_TX_x_p

ML_RX_x_n

ML_RX_x_p

ML_RX_x_n

ML_RX_x_p

Source

Connector

Tx

Rx

50

50

Vbias_Tx

50

50

Vbias_Rx

100k-1M

100k-1M

Figure 1. DisplayPort Main Link Connection Diagram