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PI2DPX2063 Datasheet(PDF) 19 Page - Diodes Incorporated

No. de pieza PI2DPX2063
Descripción Electrónicos  1.8V 20Gbps DP2.0 Linear ReDriver with AUX Listener & I2C Control
PDF  36 Pages
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Fabricante Electrónico  DIODES [Diodes Incorporated]
Página de inicio  http://www.diodes.com
Logo DIODES - Diodes Incorporated

PI2DPX2063 Datasheet(HTML) 19 Page - Diodes Incorporated

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A Product Line of
Diodes Incorporated
PI2DPX2063
19
July 2022
© 2022 Copyright Diodes Incorporated. All Rights Reserved.
PI2DPX2063
Document Number DS43839 Rev 2-2
www.diodes.com
7. In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering
bus timing.
8. Input filters on the SDA and SCL inputs suppress noise spikes of less than 50ns.
9. If VDD is switched off, I/O pins of Fast-mode and Fast-mode Plus device must not obstruct the SDA and SCL lines.
10. Special purpose device such as multiplexers and switches may exceed this capacitance because they connect multiple paths together.
Figure 12. I2C I/O Stage Noise Margin
0.9 VCC
0.7 VCC
0.3 VCC
0.4V
VOH
VIH
VIL
VOL
Driver High
Logic High
Noise Margin
Receiver
Threshold Band
Logic Low
Noise Margin
Driver Low
Characteristics of the SDA and SCL Bus Line for Standard, Fast, and Fast-mode Plus I2C-bus Device (1)
Symbol Parameter
Conditions
Standard-Mode
Fast-Mode
Fast-Mode Plus
Units
Min.
Max.
Min.
Max. Min. Max.
fSCL
SCL clock frequency
0
100
0
400
0
1000
KHz
tHD;STA Hold time (repeated) START
condition
After this period, the
first clock pulse is
generated.
4.0
0.6
0.26
µs
tLOW
LOW period of the SCL clock
4.7
1.3
0.5
µs
tHIGH
HIGH period of the SCL clock
4.0
0.6
0.26
µs
tSU;STA
Set-up time for a repeated
START condition
4.7
0.6
0.26
µs
tHD;DAT Data hold time(2)
CBUS compatible
masters
5.0
µs
I2C-Bus Devices
0(3)
(4)
0(3)
(4)
0
tSU;DAT
Data set-up time
250
100(5)
50
ns
tr
Rise time of both SDA and
SCL signals
1000
20
300
120
ns
tf
Fall time of both SDA and SCL
signals(3)(6)(7)(8)
300
20×(VDD
/5.5V)
300 20×(VDD
/5.5V)(9) 120
(8)
ns
tSU;STO
Set-up time for STOP condi-
tion
4.0
0.6
0.26
µs
tBUF
Bus free time between a STOP
and START condition
4.7
1.3
0.5
µs
Cb
Capacitive load for each bus
line(10)
400
400
550
pF
tVD;DAT Data valid time(11)
3.45(4)
0.9(4)
0.45(4)
µs



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