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HC705JJ7GRS/D Datasheet(PDF) 51 Page - NXP Semiconductors

No. de pieza HC705JJ7GRS/D
Descripción Electrónicos  Low-Cost, HC05 Core MCU in 20-Pin Package (MC68HC705JJ7) or 28-Pin Package (MC68HC705JP7)
PDF  230 Pages
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Fabricante Electrónico  NXP [NXP Semiconductors]
Página de inicio  http://www.nxp.com
Logo NXP - NXP Semiconductors

HC705JJ7GRS/D Datasheet(HTML) 51 Page - NXP Semiconductors

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Interrupts
External Interrupts
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Interrupts
With the edge- and level-sensitive trigger MOR option, a falling edge or
a low level on the IRQ/VPP pin latches an external interrupt request. The
edge- and level-sensitive trigger MOR option allows connection to the
IRQ/VPP pin of multiple wired-OR interrupt sources. As long as any
source is holding the IRQ low, an external interrupt request is present,
and the CPU continues to execute the interrupt service routine.
With the edge-sensitive-only trigger option, a falling edge on the
IRQ/VPP pin latches an external interrupt request. A subsequent
interrupt request can be latched only after the voltage level on the
IRQ/VPP pin returns to a logic one and then falls again to logic zero.
Figure 4-3. External Interrupt Logic
PA3
PA2
PA1
PA0
IRQ
LATCH
VDD
RST
IRQ VECTOR FETCH
IRQ STATUS/CONTROL REGISTER ($000D)
EXTERNAL
INTERRUPT
REQUEST
INTERNAL DATA BUS
TO BIH & BIL
INSTRUCTION
PROCESSING
R
VPP TO
USER EPROM
AND PEPROM
MASK OPTION REGISTER ($1FF1)
IRQ/VPP
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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