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HC705JJ7GRS/D Datasheet(PDF) 87 Page - NXP Semiconductors

No. de pieza HC705JJ7GRS/D
Descripción Electrónicos  Low-Cost, HC05 Core MCU in 20-Pin Package (MC68HC705JJ7) or 28-Pin Package (MC68HC705JP7)
PDF  230 Pages
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Fabricante Electrónico  NXP [NXP Semiconductors]
Página de inicio  http://www.nxp.com
Logo NXP - NXP Semiconductors

HC705JJ7GRS/D Datasheet(HTML) 87 Page - NXP Semiconductors

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Parallel Input/Output
Port B
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Parallel Input/Output
7.4.5 PB0, PBI, PB2 and PB3 Logic
The typical I/O logic shown in Figure 7-8 is used for PB0, PB1, PB2, and
PB3 pins of port B. When these port B pins are programmed as an
output, reading the port bit actually reads the value of the data latch and
not the voltage on the pin itself. When these port B pins are programmed
as an input, reading the port bit reads the voltage level on the pin. The
data latch can always be written, regardless of the state of its DDRB bit.
The operations of the PB0:3 pins are summarized in Table 7-2.
Figure 7-8. PB0:3 Pin I/O Circuit
PORT BDATA
REGISTER
BIT PBx
DATA DIRECTION
REGISTER B
BIT DDRBx
PULLDOWN
REGISTER B
BIT PDIBx
R
R
PBx
ANALOG SUBSYSTEM,
AND PROGRAMMABLE
TIMER INPUT CAPTURE
READ $0005
WRITE $0001
READ $0001
WRITE $0011
PULLDOWN
DEVICE
RESET
(PINS PB0, PB1, PB2, PB3)
WRITE $0005
MASK OPTION REGISTER ($1FF1)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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