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HC705JJ7GRS/D Datasheet(PDF) 101 Page - NXP Semiconductors

No. de pieza HC705JJ7GRS/D
Descripción Electrónicos  Low-Cost, HC05 Core MCU in 20-Pin Package (MC68HC705JJ7) or 28-Pin Package (MC68HC705JP7)
PDF  230 Pages
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Fabricante Electrónico  NXP [NXP Semiconductors]
Página de inicio  http://www.nxp.com
Logo NXP - NXP Semiconductors

HC705JJ7GRS/D Datasheet(HTML) 101 Page - NXP Semiconductors

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Parallel Input/Output
Port C (28-Pin Versions Only)
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Parallel Input/Output
7.5.4 Port C Logic
Figure 7-15 shows the I/O logic of port C.
When a port C pin is programmed as an output, reading the port bit
actually reads the value of the data latch and not the voltage on the pin
itself. When a port C pin is programmed as an input, reading the port bit
reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its DDR bit. Table 7-4 summarizes the
operations of the port C pins.
Figure 7-15. Port C I/O Circuit
PCx
PORT C DATA
REGISTER
BIT PCx
READ $0006
WRITE $0002
READ $0002
WRITE $0010
PULLDOWN
DEVICE
RESET
WRITE $0006
DATA DIRECTION
REGISTER C
BIT DDRCx
PULLDOWN
REGISTER A
BIT PDICx
R
R
MASK OPTION REGISTER ($1FF1)
HIGH SINK/SOURCE
CURRENT CAPABILITY
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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