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STM32H7B3II Datasheet(PDF) 124 Page - STMicroelectronics

No. de pieza STM32H7B3II
Descripción Electrónicos  32-bit Arm® Cortex®-M7 280 MHz MCUs, 2-Mbyte flash memory, 1.4-Mbyte RAM, 46 com. and analog interfaces, SMPS, crypto
PDF  238 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32H7B3II Datasheet(HTML) 124 Page - STMicroelectronics

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Capacitive load CL = 30 pF
In all timing tables, Tfmc_ker_ck is the kernel clock period.
Figure 36. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
Data
FMC_NE
FMC_NBL[1:0]
FMC_D[15:0]
tv(BL_NE)
th(Data_NE)
FMC_NOE
Address
FMC_A[25:0]
tv(A_NE)
FMC_NWE
tsu(Data_NE)
tw(NE)
w(NOE)
t
tv(NOE_NE)
th(NE_NOE)
th(Data_NOE)
th(A_NOE)
th(BL_NOE)
tsu(Data_NOE)
FMC_NADV
(1)
tv(NADV_NE)
tw(NADV)
FMC_NWAIT
tsu(NWAIT_NE)
th(NE_NWAIT)
1.
Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
Table 72. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
Symbol
Parameter
Min(1)
Max(1)
Unit
tw(NE)
FMC_NE low time
3Tfmc_ker_ck − 1
3Tfmc_ker_ck +1
ns
tv(NOE_NE)
FMC_NEx low to FMC_NOE low
0
0.5
tw(NOE)
FMC_NOE low time
2Tfmc_ker_ck − 1
2Tfmc_ker_ck + 1
th(NE_NOE)
FMC_NOE high to FMC_NE high hold time
0
-
tv(A_NE)
FMC_NEx low to FMC_A valid
-
0.5
th(A_NOE)
Address hold time after FMC_NOE high
0
-
tsu(Data_NE)
Data to FMC_NEx high setup time
13
-
STM32H7B3xI
Operating conditions
DS13139 - Rev 8
page 124/238



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