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STM32H7B3II Datasheet(PDF) 173 Page - STMicroelectronics |
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STM32H7B3II Datasheet(HTML) 173 Page - STMicroelectronics |
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173 / 238 page ![]() Figure 69. SPI timing diagram - slave mode and CPHA = 1(1) MSv69585V1 SS input CPHA=1 CPOL=0 CPHA=1 CPOL=1 MISO output MOSI input tsu(SI) th(SI) tw(SCKL) tw(SCKH) tsu(SS) tc(SCK) ta(SO) tv(SO) First bit OUT Next bits OUT Next bits IN Last bit OUT th(SO) tr(SCK) tf(SCK) th(SS) tdis(SO) First bit IN Last bit IN 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. Figure 70. SPI timing diagram - master mode(1) MSv69586V1 CPHA=0 MOSI OUTPUT MISO INPUT CPHA=0 LSB OUT LSB IN CPOL=0 CPOL=1 BIT1 OUT SS input tc(SCK) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) th(MI) High CPHA=1 CPHA=1 CPOL=0 CPOL=1 tsu(MI) tv(MO) th(MO) MSB IN BIT6 IN MSB OUT 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. 6.3.36.4 I2S Interface characteristics Unless otherwise specified, the parameters given in Table 119 for I2S are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 22. General operating conditions and Section 6.3.1 , with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 STM32H7B3xI Operating conditions DS13139 - Rev 8 page 173/238 |
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