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STM32H7B3II Datasheet(PDF) 170 Page - STMicroelectronics |
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STM32H7B3II Datasheet(HTML) 170 Page - STMicroelectronics |
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170 / 238 page ![]() Symbol Parameter Conditions Min Typ Max(1) Unit th(RX) Data input hold time Master mode ns 0 - - Slave mode 1.5 - - tv(TX) Data output valid time Slave mode transmitter mode, 1.62 V < VDD < 3.6 V - 15.5 22 Slave mode transmitter mode, 2.7 V < VDD < 3.6 V - 15.5 17 Master mode - 1.5 2 th(TX) Data output hold time Slave mode 12 - - Master mode 1 - - 1. At VOS1, these values are degraded by up to 5 %. Figure 66. USART timing diagram in Master mode MSv65386V1 CPHA=0 TX OUTPUT RX INPUT CPHA=0 LSB OUT LSB IN CPOL=0 CPOL=1 BIT1 OUT NSS input tc(SCK) tw(SCKH) tw(SCKL) tr(SCK)/tf(SCK) th(RX) High CPHA=1 CPHA=1 CPOL=0 CPOL=1 tsu(RX) tv(TX) th(TX) MSB IN BIT6 IN MSB OUT 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. STM32H7B3xI Operating conditions DS13139 - Rev 8 page 170/238 |
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