9P960

DUAL CHANNEL DDRII/III ZERO DELAY BUFFER

IDT® DUAL CHANNEL DDRII/III ZERO DELAY BUFFER

4

9P960

REV A 051811

Timing

Switching Characteristics1

TA = 0 - 70°C; Supply Voltage AVDD1.8, VDD1.8/1.5 = 1.8 V +/- 0.1V (unless otherwise stated)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Max clock frequency

freqop

1.8V+0.1V @ 25°C

150

600

MHz

Application Frequency

Range

freq

Ap p

1.8V+0.1V @ 25°C

160

533

MHz

Input clock duty cycle

d

tin

40

60

%

CLK stabilization

T

ST AB

15

µs

TA = 0 - 70°C; Supply Voltage AVDD1.8, VDD1.8/1.5 = 1.8 V +/- 0.1V (unless otherwise stated)

PARAMETER

SYMBOL

COND ITION

MIN

TYP

MAX

UNITS

Output enable time

ten

OE to any output

8

ns

Output disable time

t

dis

OE to any output

8

ns

Period jitter

tjit (pe r)

-30

30

ps

Half-period jitter

tjit(hpe r)

-40

40

ps

Input Clock

1

2.5

4

v/ns

Output Enable (OE), (OS)

0.5

v/ns

Output clock slew rate

SLr1(o)

1.5

2.5

3

v/ns

tjit(cc+)

40

ps

t

jit(cc- )

-40

ps

Dynamic Phase Offset

t( )d yn

-20

20

ps

Static Phase Offset

t

(spo)

-60

0

60

ps

Output to Output Skew

t

skew

100

ps

SSC modulation frequency

f

SSCMOD

30.00

33

kHz

SSC clock input frequency

deviation

fSSC%

0.00

-0.50

%

1. Switching characteristics guaranteed for application frequency range.

Notes:

Input slew rate

SLr1(i)

Cycle-to-cycle jitter

PLL will track SSC and

meet dynamic phase offset

in the specified range.