ICS9P960 datasheet(1/13 Pages) RENESAS

No. de pieza	ICS9P960

Descripción Electrónicos	DUAL CHANNEL DDRII/III ZERO DELAY BUFFER

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DATASHEET

DUAL CHANNEL DDRII/III ZERO DELAY BUFFER

9P960

IDT® DUAL CHANNEL DDRII/III ZERO DELAY BUFFER

1

9P960

REV A 051811

Recommended Application

Dual DDR zero delay buffer

Features/Benefits

• High performance, low jitter zero delay buffer

• I2C for functional and output control

• Dual bank 1-6 differential clock distribution

• 2 separate feedback in & out for input to output

synchronization for each bank

• Supports up to 4 DDR DIMMs

• Supports up to DDRII - 1066MHz

• Supports up to DDRIII (1.8V core) - 1333MHz

• Output-to-output skew: <100ps

Pin Configuration

Block Diagram

DDRA T0 1

48 FB_OUTA

DDRA C0 2

47 FB_INTA

DDRA T1 3

46 VDD1.8/1.5

DDRA C1 4

45 CLK_INTA _T

DDRA T2 5

44 CLK_INTA _C

DDRA C2 6

43 GND

GND 7

42 DDRAT3

VDD1.8/1.5 8

41 DDRAC3

AGND 9

40 DDRAT4

AVDD1.8 10

39 DDRAC4

SCLK 11

38 DDRAT5

SDATA 12

37 DDRAC5

VDD1.8/1.5 13

36 VDD1.8/1.5

DDRB T0 14

35 GND

DDRB C0 15

34 AVDD1.8

DDRB T1 16

33 AGND

DDRB C1 17

32 GND

DDRB T2 18

31 VDD1.8/1.5

DDRB C2 19

30 DDRBT5

CLK_INTB _T 20

29 DDRBC5

CLK_INTB _C 21

28 DDRBT4

GND 22

27 DDRBC4

FB_INTB 23

26 DDRBT3

FB_OUTB 24

25 DDRBC3

48-SSOP

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ICS9P960 Datasheet(PDF) 1 Page - Renesas Technology Corp

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