P9242-R3/RB Datasheet

© 2019 Integrated Device Technology, Inc.

10

May 17, 2019

Symbol

Description

Conditions/Notes

Min

Typical

Max

Units

LDO18[b]

VLDO18

1.8V LDO Regulator

COUT = 1µF, VVIN_LDO = 5.5V

1.71

1.8

1.89

V

LDO33[b]

VLDO33

3.3V LDO Regulator

COUT = 1µF, VVIN_LDO = 5.5V

3.15

3.3

3.45

V

PREG

VPREG

5V LDO Regulator

5

V

Thermal Shutdown

TSD

Thermal Shutdown

Threshold rising

140

°

C

Threshold falling

120

°

C

Analog Input Pins Input Current Leakage (TS, VCOIL)

ILKG

Leakage Current

-1

1

µA

Open-Drain Pins Output Logic Levels (LED1, LED2, SCL, SDA)

VOH

Output Logic HIGH

4

V

VOL

Output Logic LOW

I = 8mA

0.5

V

Digital Input/Output Pins Logic Levels

VIH

Input Voltage HIGH Level

0.7∗VDDIO

V

VIL

Input Voltage LOW Level

0.3∗VDDIO

V

ILKG

Leakage Current

1

µA

VOH

Output Logic HIGH

I = 8mA, VDDIO = 3.3V

2.4

V

VOL

Output Logic LOW

I = 8mA, VDDIO = 3.3V

0.5

V

I2C Interface (SCL, SDA)

fSCL_SLV

Clock Frequency

As I2C slave

400

kHz

CB

Capacitive Load

For each bus line

100

pF

CBIN

SCL, SDA Input Capacitance

5

pF

ILKG

Input Leakage Current

V = GND and 3.3V

-1

1

µA

[a] The input voltage operating range is dependent upon the type of transmitter power stage (full-bridge, half-bridge) and transmitting coil

inductance. WPC specifications should be consulted for appropriate input voltage ranges by end-product type.

[b] Do not externally load. For internal biasing only.

[c] A 20mΩ, 1% or better sense resistor and a 4.7Ω, 1% input filter resistor are required to meet the FOD specification.