ADM1177

Preliminary Technical Data

Rev. PrD | Page 6 of 16

PIN CONFIGURATIONS

1

2

3

4

ADM1177

TOP VIEW

(NOT TO SCALE)

Vcc

ADR

SDA

GATE

ON

TIMER

SENSE

SS

GND

5

SCL

10

9

8

7

6

Figure 3. Pin Configurations

PIN FUNCTIONAL DESCRIPTIONS

Table 3.

Pin No.

Name

Description

1

VCC

Positive supply input pin. The operating supply voltage range is between 3.15 V to 14 V. An undervoltage

lockout (UVLO) circuit resets the ADM1177 when a low supply voltage is detected.

2

SENSE

Current sense input pin. A sense resistor between the VCC and SENSE pins sets the analog current limit. The

mV or below.

3

ON

Undervoltage input pin. Active high pin. An internal ON comparator has a trip threshold of 1.3 V and the

output of this comparator is used as an enable for the hotswap operation. With an external resistor divider

from VCC to GND, this pin can be used to enable the hotswap operation one a specific voltage on VCC, giving

an undervoltage function.

4

GND

Chip Ground Pin

5

TIMER

Timer pin. An external capacitor CTIMER sets a 270 ms/µF initial timing cycle delay and a 21.7 ms/µF fault

delay. The GATE pin turns off whenever the TIMER pin is pulled beyond the upper threshold. An overvoltage

detection with an external zener can be used to force this pin high.

6

SCL

7

SDA

8

ADR

9

SS

Soft-Start Pin. This pin controls the reference on the current sense amplifier. A 10 µA current source charges

this pin at startup. A capacitor on this pin will then set the slope of the initial current ramp. This pin can also

be driven to a voltage to alter the reference directly, thereby adjusting the current limit level.

10

GATE

GATE Output Pin. This pin is the high side gate drive of an external N-channel FET. This pin is driven by the FET

drive controller which utilises a charge pump to provide a 12 µA pull-up current to charge the FET gate pin.

The FET drive controller regulates to a maximum load current (100 mV through the sense resistor) by

modulating the GATE pin.