ICS9P935 datasheet(1/14 Pages) RENESAS

No. de pieza	ICS9P935

Descripción Electrónicos	DDR I/DDR II Phase Lock Loop Zero Delay Buffer

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ICS9P935

IDTTM/ICSTM

DDR I/DDR II Phase Lock Loop Zero Delay Buffer

ICS9P935

REV H

12/1/08

DDR I/DDR II Phase Lock Loop Zero Delay Buffer

DATASHEET

1

FB_IN

SCLK

SDATA

CLK_INT

CLK_INC

Control

Logic

FB_OUT

DDRT0

DDRC0

DDRT1

DDRC1

DDRT2

DDRC2

DDRT3

DDRC3

DDRT4

DDRC4

DDRT5

DDRC5

PLL

Description

Output Features

DDR I/DDR II Zero Delay Clock Buffer

•

Low skew, low jitter PLL clock driver

•

Max frequency supported = 400MHz (DDRII 800)

•I

2C for functional and output control

•

Feedback pins for input to output synchronization

•

Spread Spectrum tolerant inputs

•

Programmable skew through SMBus

•

Frequency defect control thorugh SMBus

•

Individual output control programmable through SMBus

Funtional Block Diagram

Key Specifications

•

CYCLE - CYCLE jitter: <100ps

•

OUTPUT - OUTPUT skew: <100ps

•

DUTY CYCLE: 48% - 52%

•

28-pin SSOP package

•

Available in RoHS compliant packaging

•

Operates @ 2.5V or 1.8V

Pin Configuration

DDRC0 1

28 GND

DDRT0 2

27 DDRC5

VDD2.5/1.8 3

26 DDRT5

DDRT1 4

25 VDD2.5/1.8

DDRC1 5

24 GND

GND 6

23 DDRC4

VDDA2.5/1.8 7

22 DDRT4

GND 8

21 VDD2.5/1.8

CLK_INT 9

20 SDATA

CLK_INC 10

19 SCLK

VDD2.5/1.8 11

18 FB_IN

DDRT2 12

17 FB_OUT

DDRC2 13

16 DDRT3

GND 14

15 DDRC3

28-SSOP/TSSOP

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ICS9P935 Datasheet(PDF) 1 Page - Renesas Technology Corp

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