WMS7204

Publication Release Date: January 2003

- 11 -

Revision 1.0

The WMS7204 contains a four-wire SPI interface:

•

SDO (Serial Data Output) Used for reading out the internal register contents and for daisy

chaining multiple devices.

•

SDI (Serial Data Input) Used for clocking in commands and potentiometer settings.

•

CS (Chip Select) This pin must be pulled LOW before starting to send a command and pulled

HIGH to signal the end of the command. This pin can be used to control multiple devices on

the bus.

•

CLK (Clock) The SDI bits are shifted in on the rising edge of the clock and SDO data is

shifted out on the falling edge of the clock.

The key features of this interface include:

•

Independently programmable Read & Write to all registers

•

Direct parallel refresh of all Tap registers from corresponding internal NVMEM registers

•

Increment and decrement instruction for each Tap register

•

Nonvolatile storage of the present Tap register values into one of the four NVMEM registers

available to each channel

•

Configurable output buffer amplifier to allow both the functions of a potentiometer and a

variable resistor

•

Four 9-bit non-volatile registers store four preset wiper positions and the first one will be

recalled to set the wiper position during power up.

The serial interface uses an SPI compatible uniform 24-bit word format as shown below. This format is

used for all members of the WMS720x family. The data is sent MSB first.

TABLE 2 – 24-BIT DATA WORD FORMAT

MSB

LSB

C3

C2

C1

C0

A3

A2

A1

A0

X

X

X

X

X

X

X

D8

D7

D6

D5

D4

D3

D2

D1

D0

C3-C0 are the command bits that control the operation of the digital potentiometer according to the

command instructions shown in the Instruction Set in Table 5 in Section 7.7.

A1 and A0 are the address bits that determine which channel is activated, as shown in the table

below.