CS5535 datasheet(115/555 Pages) NSC

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4.10 SYSTEM MANAGEMENT BUS CONTROLLER

The System Management Bus (SMB) Controller is a two-

wire synchronous serial interface compatible with the Sys-

tem Management Bus physical layer. The SMB Controller

is also compatible with Intel's SMBus and Philips’ I2C. The

SMB Controller can be configured as a bus master or

slave, and can maintain bidirectional communication with

both multiple master and slave devices. As a slave device,

the SMB Controller may issue a request to become the bus

master.

The SMB Controller allows easy interfacing to a wide range

low-cost

memories

and

I/O

devices,

including:

EEPROMs, SRAMs, timers, ADC, DAC, clock chips, and

peripheral drivers.

This chapter describes the general SMB Controller func-

tional block. A device may include a different implementa-

tion.

A block diagram of the System Management Bus (SMB)

Controller is shown Figure 4-22.

The SMB Controller is upward compatible with previous

industry standard two-wire interfaces as detailed in Table 4-

17 on page 116.

The SMB Controller’s protocol uses a two-wire interface for

bidirectional communication between the ICs connected to

the bus. The two interface lines are the Serial Data Line

(SDL) and the Serial Clock Line (SCL). These lines should

be connected to a positive supply via an internal or external

pull-up resistor, and remain high even when the bus is idle.

Each IC has a unique address and can operate as a trans-

mitter or a receiver (though some peripherals are only

receivers).

During data transactions, the master device initiates the

transaction, generates the clock signal, and terminates the

transaction. For example, when the SMB Controller ini-

tiates a data transaction with an attached SMB compliant

peripheral, the SMB Controller becomes the master. When

the peripheral responds and transmits data to the SMB

Controller, their master/slave (data transaction initiator and

clock generator) relationship is unchanged, even though

their transmitter/receiver functions are reversed.

Figure 4-22. SMB Block Diagram

Data In

Local Bus Interface

CCU

PIC

Busy

IRQ

Clock

I/O Enable

Data Out

Clock Out

SMB Controller

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