CS5535 datasheet(117/555 Pages) NSC

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SMB Controller Functional Description (Continued)

4.10.1 Data Transactions

One data bit is transferred during each clock pulse. Data is

sampled during the high state of the serial clock (SCL).

Consequently, throughout the clock’s high period, the data

should remain stable (see Figure 4-23). Any changes on

the SDA line during the high state of SCL and in the middle

of a transaction aborts the current transaction. New data

should be sent during the low SCL state. This protocol per-

mits a single data line to transfer both command/control

information and data, using the synchronous serial clock.

Each data transaction is composed of a START condition,

a number of byte transfers (set by the software), and a

STOP condition to terminate the transaction. Each byte is

transferred with the most significant bit first, and after each

byte (8 bits), an Acknowledge signal must follow. The fol-

lowing subsections provide further details of this process.

During each clock cycle, the slave can stall the master

while it handles the previous data or prepares new data.

This can be done for each bit transferred, or on a byte

boundary, by the slave holding SCL low to extend the clock-

low period. Typically, slaves extend the first clock cycle of a

transfer if a byte read has not yet been stored, or if the next

byte to be transmitted is not yet ready. Some microcontrol-

lers, with limited hardware support for SMB, extend the

SMB after each bit, thus allowing the software to handle

this bit.

Figure 4-23. SMB Bit Transfer

4.10.1.1 START and STOP Conditions

The SMB master generates START and STOP conditions

(control codes). After a START condition is generated, the

bus is considered busy and retains this status for a certain

time after a STOP condition is generated. A high-to-low

transition of the data line (SDA) while the clock (SCL) is

high indicates a START condition. A low-to-high transition

of the SDA line while the SCL is high indicates a STOP

condition (see Figure 4-24).

In addition to the first START condition, a repeated START

condition can be generated in the middle of a transaction.

This allows another device to arbitrate the bus, or a change

in the direction of data transfer.

Figure 4-24. SMB START and STOP Conditions

4.10.1.2 Acknowledge (ACK) Cycle

The ACK cycle consists of two signals: the ACK clock pulse

sent by the master with each byte transferred, and the ACK

signal sent by the receiving device (see Figure 4-25).

The master generates the ACK clock pulse on the ninth

clock pulse of the byte transfer. The transmitter releases

the SDA line (permits it to go high) to allow the receiver to

send the ACK signal. The receiver must pull down the SDA

line during the ACK clock pulse, signalling that it has cor-

rectly received the last data byte and is ready to receive the

next byte. Figure 4-26 illustrates the ACK cycle.

Figure 4-25. SMB Data Transaction

SDA

SCL

Data Line

Stable:

Data Valid

Change

of Data

Allowed

SDA

SCL

START

Condition

STOP

Condition

START

Condition

STOP

Condition

SDA

SCL

MSB

ACK

12 3 - 6

23 - 8

Acknowledge

Signal From Receiver

Byte Complete

Interrupt Within

Receiver

Clock Line Held

Low by Receiver

While Interrupt

is Serviced

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