AT83251G2D datasheet(21/77 Pages) ATMEL

21 / 77 page

AT/TSC8x251G2D

4135F–8051–11/06

Instruction Set

Summary

This section contains tables that summarize the instruction set. For each instruction

there is a short description, its length in bytes, and its execution time in states (one state

time is equal to two system clock cycles). There are two concurrent processes limiting

the effective instruction throughput:

•

Instruction Fetch

•

Instruction Execution

Table 20 to Table 32 assume code executing from on-chip memory, then the CPU is

fetching 16-bit at a time and this is never limiting the execution speed.

If the code is fetched from external memory, a pre-fetch queue will store instructions

ahead of execution to optimize the memory bandwidth usage when slower instructions

are executed. However, the effective speed may be limited depending on the average

size of instructions (for the considered section of the program flow). The maximum aver-

age instruction throughput is provided by Table 14 depending on the external memory

configuration (from Page Mode to Non-Page Mode and the maximum number of wait

states). If the average size of instructions is not an integer, the maximum effective

throughput is found by pondering the number of states for the neighbor integer values.

Table 14.

Minimum Number of States per Instruction for given Average Sizes

If the average execution time of the considered instructions is larger than the number of

states given by Table 14, this larger value will prevail as the limiting factor. Otherwise,

the value from Table 14 must be taken. This is providing a fair estimation of the execu-

tion speed but only the actual code execution can provide the final value.

Notation for Instruction

Operands

Table 15 to Table 19 provide notation for Instruction Operands.

Table 15.

Notation for Direct Addressing

Average size

of Instructions

(bytes)

Page Mode

(states)

Non-page Mode (states)

0 Wait

State

1 Wait

State

2 Wait States 3 Wait States 4 Wait States

Direct

Address

Description

C251

C51

dir8

A direct 8-bit address. This can be a memory address (00h-7Fh) or a

SFR address (80h-FFh). It is a byte (default), word or double word

depending on the other operand.

dir16

A 16-bit memory address (00:0000h-00:FFFFh) used in direct

addressing.

3–

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