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AT83251G2D Datasheet(PDF) 53 Page - ATMEL Corporation |
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AT83251G2D Datasheet(HTML) 53 Page - ATMEL Corporation |
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53 / 77 page ![]() 53 AT/TSC8x251G2D 4135F–8051–11/06 Timings Table 46. Serial Port AC Timing -Shift Register Mode; VDD = 2.7 to 5.5 V, TA = -40 to 85 °C Note: 1. For high speed versions only. Waveforms Figure 17. Serial Port Waveforms - Shift Register Mode Note: 1. TI and RI are set during S1P1 of the peripheral cycle following the shift of the eight bit. Symbol Parameter 12 MHz 16 MHz 24 MHz(1) Unit Min Max Min Max Min Max TXLXL Serial Port Clock Cycle Time 998 749 500 ns TQVXH Output Data Setup to Clock Rising Edge 833 625 417 ns TXHQX Output Data hold after Clock Rising Edge 165 124 82 ns TXHDX Input Data Hold after Clock Rising Edge 000 ns TXHDV Clock Rising Edge to Input Data Valid 974 732 482 ns TXLXL TXHDV TXHDX TQVXH TXHQX Set TI(1) Set RI(1) Valid Valid Valid Valid Valid Valid Valid Valid RXD (In) RXD (Out) TXD 0 1 2 3 4 5 6 7 |
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