LTM4650-2 datasheet(27/36 Pages) AD

27 / 36 page

LTM4650-2

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

Layout Checklist/Example

The high integration of LTM4650-2 makes the PCB board

layout very simple and easy. However, to optimize its elec-

trical and thermal performance, some layout consider-

ations are still necessary.

• Use large PCB copper areas for high current paths,

including VIN, GND, VOUT1 and VOUT2. It helps to mini-

mize the PCB conduction loss and thermal stress.

• Place high-frequency ceramic input and output capaci-

tors next to the VIN, PGND and VOUT pins to minimize

high-frequency noise.

• Place a dedicated power ground layer underneath

the unit.

• To minimize the via conduction loss and reduce module

thermal stress, use multiple vias for interconnection

between the top layer and other power layers.

• Do not put via directly on the pad, unless they are

capped or plated over.

• Use a separated SGND ground copper area for com-

ponents connected to signal pins. Connect the SGND

to the GND underneath the unit.

• For parallel modules, tie the VOUT, VFB, and COMP pins

together. Use an internal layer to closely connect these

pins together. The TRACK pin can be tied to a common

capacitor for regulator soft-start.

• Bring out test points on the signal pins for monitoring.

Figure 23 gives a good example of the recommended

layout. LGA and BGA PCB layouts are identical, with

the exception of circle pads for BGA (see Package

Description section).

Figure 23. Recommended PCB Layout

GND

CNTRL

VOUT1

COUT1

COUT2

VOUT2

VIN

CIN1

CIN2

46502 F23

SGND

LTM4650-2 Datasheet(PDF) 27 Page - Analog Devices

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