LTM4650 datasheet(10/36 Pages) AD

10 / 36 page

LTM4650-2

Rev. 0

For more information www.analog.com

The typical LTM4650-2 application circuit is shown in

Figure 24. External component selection is primarily

determined by the maximum load current and output volt-

age. See Table 4 for specific external capacitor require-

ments for particular applications.

OUTPUT TOTAL DC ACCURACY AND AC TRANSIENT

PERFORMANCE

In modern ASIC and FPGA power supply designs, a tight

total voltage regulation window, ±3% for example, is

required of the supply powering the core and periphery. To

meet this requirement, the supply’s DC voltage variance

plus any AC voltage variation that may occur during any

load step transient must fall within this allowed window.

The DC voltage variance is determined by the accuracies

of the supply’s reference voltage, resistor divider, load

regulation and line regulation over the operating tempera-

ture range. The AC voltage variance is determined by the

supply’s output voltage overshoot and undershoots in

response to a load transient condition for a given output

capacitor network.

Figure 2 shows a typical load step transient response

waveform and DC voltage accuracy variance. For a given

allowable voltage regulation window, a tighter DC volt-

age accuracy allows more margin for the AC variation

due to a load transient response. This increased margin

for AC variation allows for a reduction in the total out-

put capacitance required to meet the regulation window

requirement. This allows for a reduced total solution cost

and footprint area.

APPLICATIONS INFORMATION

For example, in an FPGA core voltage application, for a 12V

input, 0.9V output at 72A design, a total overall ±3% total

voltage regulation window is required in responding to a

25% load step transient. Figure 3 illustrates the benefit of

overall output capacitor reduction versus improved total

DC accuracy by using 100µF ceramic output capacitors.

Figure 2. Typical Load Step Transient Response with DC Voltage

Accuracy Variance

ALLOWABLE

REGULATION

WINDOW

DC ACCURACY

LOAD STEP

AC OVERSHOOT

AC UNDERSHOOT

46502 F02

TOTAL DC ACCURACY (%)

5000

4000

3000

2000

1000

4500

3500

2500

1500

500

0.8

1.5

46502 F03

2.0

1.2

2200

3200

2600

4700

Figure 3. Overall Output Capacitor vs Total DC Accuracy

VIN to VOUT Step-Down Ratios

There are restrictions in the maximum VIN and VOUT step-

down ratio that can be achieved for a given input voltage.

Each output of the LTM4650-2 is capable of a 98% duty

cycle, but the VIN to VOUT minimum dropout is still shown

as a function of its load current and will limit output cur-

rent capability related to the high duty cycle on the top

side switch. Minimum on-time tON(MIN) is another consid-

eration in operating at a specified duty cycle while operat-

ing at a certain frequency because tON(MIN) < D/fSW, where

D is the duty cycle and fSW is the switching frequency.

tON(MIN) is specified in the Electrical parameters as 90ns.

Output Voltage Programming

The PWM controller has an internal 0.6V reference volt-

age. As shown in the Simplified Block Diagram, a 60.4k

internal feedback resistor connects between the VOUTS1 to

VFB1 and VOUTS2 to VFB2. These pins must be connected

to their respective outputs for proper feedback regulation.

Overvoltage can occur if these VOUTS1 and VOUTS2 pins are

left floating when used as individual regulators, or at least

one of them is used in paralleled regulators. The output

voltage will default to 0.6V with no feedback resistor on

LTM4650 Datasheet(PDF) 10 Page - Analog Devices

LTM4650 Datasheet(HTML) 10 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Descarga

Enlace URL