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AS73211 Datasheet(PDF) 61 Page - OSRAM GmbH |
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AS73211 Datasheet(HTML) 61 Page - OSRAM GmbH |
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61 / 66 page ![]() Document Feedback AS73211 Soldering & Storage Information Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 60 12 Soldering & Storage Information The die-attach pad 17 (exposed pad) of the QFN16 package must be connected to analog ground VSSA on PCB. Realize this before soldering by a conductive adhesive and bonding this pad of the sensor backside to a ground pad on the PCB. According to the JEDEC standard, the QFN16 package has been tested and has demonstrated the ability to be reflow-soldered to a PCB substrate. The solder reflow profile describes the expected maximum heat exposure of components during the solder reflow process of product on a PCB. Temperature is measured on top of component. The component should be limited to a maximum of three passes through this solder reflow profile. Figure 60: Profile Features According to JEDEC IPC/JEDEC J-STD-020D.1 (Pb-Free) RECOMMENDED DATA Time [s] from 150°C to 200°C (preheat) 60 – 120 100 Average ramp-up rate [°C/s] (200°C to peak temperature) maximum 3.0 0.5 – 1.0 Liquidus temperature [°C] Time [s] above liquidus (217°C) 217 60 – 150 217 110 Peak package body temperature [°C] maximum 260 ≤ 260 Time [s] within 5°C of the classification temperature minimum 30 35 – 45 Average ramp-down rate [°C/s] (peak temperature to 200°C) maximum 6.0 3.0 Time [s] from 25°C to peak temperature maximum 480 350 Do not exceed the recommended values shown in the table or following figure. For further information, see the JEDEC standard J-STD-020D.1. Figure 61: Solder Reflow Profile Graph Time 25 °C To Peak tS Time → TL TP 25 Tsmin Tsmax tL Preheat Area Max. Ramp Up Rate = 3 °C/s Max. Ramp Down Rate = 6 °C/s tP TC –5 °C Supplier tP Supplier TP ≥ TC User tP User TP ≤ TC TC TC –5 °C |
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