MPC880CZP66 datasheet(68/92 Pages) FREESCALE

68 / 92 page

MPC885/MPC880 Hardware Specifications, Rev. 3

Freescale Semiconductor

CPM Electrical Characteristics

Table 29 provides the I2C (SCL > 100 KHz) timings.

210

SDL/SCL fall time

—

300

211

Stop condition setup time

4.7

—

µs

1 SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) × pre_scaler × 2).

The ratio SyncClk/(BRGCLK/pre_scaler) must be greater or equal to 4/1.

Table 29. I2C Timing (SCL > 100 KHZ)

Num

Characteristic

Expression

All Frequencies

Unit

Min

Max

200

SCL clock frequency (slave)

fSCL

BRGCLK/48

200

SCL clock frequency (master) 1

1 SCL frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) × pre_scaler × 2).

The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1.

fSCL

BRGCLK/16512

BRGCLK/48

202

Bus free time between transmissions

—

1/(2.2

× fSCL)

—

203

Low period of SCL

—

1/(2.2

× fSCL)

—

204

High period of SCL

—

1/(2.2

× fSCL)

—

205

Start condition setup time

—

1/(2.2

× fSCL)

—

206

Start condition hold time

—

1/(2.2

× fSCL)

—

207

Data hold time

—

208

Data setup time

—

1/(40

× fSCL)

—

209

SDL/SCL rise time

—

1/(10

× fSCL)

210

SDL/SCL fall time

—

1/(33

× fSCL)

211

Stop condition setup time

—

1/2(2.2

× fSCL)

—

Table 28. I2C Timing (SCL < 100 KHZ) (continued)

Num

Characteristic

All Frequencies

Unit

Min

Max

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