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MPC8540CVT667JC Datasheet(PDF) 65 Page - Freescale Semiconductor, Inc |
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MPC8540CVT667JC Datasheet(HTML) 65 Page - Freescale Semiconductor, Inc |
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65 / 104 page  MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 65 RapidIO Figure 41 shows the definitions of the data to clock static skew parameter tSKEW,PAIR and the data valid window parameter DV. The data and frame bits are those that are associated with the clock. The figure applies for all zero-crossings of the clock. All of the signals are differential signals. VD represents VOD for the transmitter and VID for the receiver. The center of the eye is defined as the midpoint of the region in which the magnitude of the signal voltage is greater than or equal to the minimum DV voltage. Figure 41. Data to Clock Skew Figure 42 shows the definition of the data to data static skew parameter tDPAIR and how the skew parameters are applied. Figure 42. Static Skew Diagram VD Clock x tSKEW,PAIR 1.0 UI Nominal 0.5 UI 0.5 DV 0.5 DV Eye Opening DV VHDmim VHDmim VD = 0 V VD = 0 V VD Clock x D[0:7]/D[8:15], FRAME CLK0 (CLK1) 1.0 UI Nominal 0.5 UI tDPAIR tSKEW,PAIR Center Point for Clock D[0:7]/D[8:15], FRAME Center point of the data valid window of the latest allowed data bit for data grouped late with respect to clock Center point of the data valid window of the earliest allowed data bit for data grouped late with respect to clock |
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