MPC8540CVT667JC datasheet(10/104 Pages) FREESCALE

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MPC8540 Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8540.

Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD

The MPC8540 core voltage must always be provided at nominal 1.2 V (see Table 2 for actual

recommended core voltage). Voltage to the processor interface I/Os are provided through separate sets of

supply pins and must be provided at the voltages shown in Table 2. The input voltage threshold scales with

respect to the associated I/O supply voltage. OVDD and LVDD based receivers are simple CMOS I/O

circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses a

single-ended differential receiver referenced the externally supplied MVREF signal (nominally set to

GVDD/2) as is appropriate for the SSTL2 electrical signaling standard.

Input voltage

DDR DRAM signals

MVIN

GND to GVDD

DDR DRAM reference

MVREF

GND to GVDD/2

Three-speed Ethernet signals

LVIN

GND to LVDD

PCI/PCI-X, local bus, RapidIO,

10/100 Ethernet, MII

management, DUART,

SYSCLK, system control and

power management, I2C, and

JTAG signals

OVIN

GND to OVDD

Die-junction temperature

0 to 105

•C

Table 2. Recommended Operating Conditions (continued)

Characteristic

Symbol

Recommended

Value

Unit

GND

GND – 0.3 V

GND – 0.7 V

Not to Exceed 10%

G/L/OVDD + 20%

G/L/OVDD

G/L/OVDD + 5%

of tSYS

tSYS refers to the clock period associated with the SYSCLK signal.

VIH

VIL

Note:

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