7

Rev. 08/19/05

SP6128A Low Voltage, Synchronous Step Down PWM Controller

© Copyright 2005 Sipex Corporation

SP6128A OVER CURRENT (HICCUP MODE)

Test Conditions

V

V

A more detailed description of the waveform is shown below.

Over Current Protection

Over current protection on the SP6128A is imple-

mented through detection of an excess voltage

condition across the high side NMOS switch

during conduction. This is typically referred to

need of an external sense resistor. The over

current comparator charges an internal sam-

discharge/charge current ratio on the sampling

capacitor is about 2%. Therefore, provided that

the over current condition persists, the capacitor

voltage will be pumped up during each time GH

switches high. This voltage will trigger an over

current condition upon reaching a CMOS in-

verter threshold. There are many advantages to

this approach. First, the filtering action of the

gated scheme protects against false and undesir-

able triggering that could occur during a minor

transient overload condition or supply line noise.

Furthermore, the total amount of time to trigger

the fault depends on the on-time of the high side

NMOS switch. Fifteen, 1

µs pulses are equiva-

lent to thirty, 500ns pulses or one, 15

µs pulse,

however, depending on the period, each sce-

nario takes a different amount of total time to

trigger a fault. Therefore, the fault becomes an

indicator of average power in the high side

BST = 5.0V

SWN - tied to GND through 1k Resistor

COMP – released from GND

Internal SSTART

pops to ~ internal

SSTART voltage +0.7V

Internal SSTART rises until

to attempt RESTART

COMP Clamps

~ 3V

After pop, COMP

retains internal

SSTART slope

ENABLE

Part

Attempt

RESTART

5µA PULLUP slope to 0.3V;

35µA PULLUP to 0.7V

Overcurrent Detected

Fault Mode Enabled

COMP

OPERATION: continued