SST25WF080B datasheet(5/44 Pages) MICROCHIP

5 / 44 page

 2013-2022 Microchip Technology Inc. and its subsidiaries

DS20005164H-page 5

SST25WF080B

3.0

MEMORY ORGANIZATION

The SST25WF080B SuperFlash memory arrays are

organized in 256 uniform 4-Kbyte sectors, with 16

64-Kbyte overlay erasable blocks.

FIGURE 3-1:

MEMORY MAP

4.0

DEVICE OPERATION

SST25WF080B is accessed through the SPI (Serial

Peripheral Interface) bus compatible protocol. The SPI

bus consist of four control lines; Chip Enable (CE#) is

used to select the device, and data is accessed through

the Serial Data Input (SI), Serial Data Output (SO), and

Serial Clock (SCK).

The SST25WF080B supports both Mode 0 (0,0) and

Mode 3 (1,1) of SPI bus operations. The difference

between the two modes, as shown in Figure 4-1, is the

state of the SCK signal when the bus client is in Stand-

by mode and no data is being transferred. The SCK sig-

nal is low for Mode 0 and SCK signal is high for Mode

3. For both modes, the Serial Data In (SI) is sampled at

the rising edge of the SCK clock signal and the Serial

Data Output (SO) is driven after the falling edge of the

SCK clock signal.

FIGURE 4-1:

SPI PROTOCOL

Top of Memory Block

00FFFFH

00F000H

000FFFH

000000H

001FFFH

001000H

Bottom of Memory Block

01FFFFH

01F000H

01FFFFH

010000H

0FFFFFH

0FF000H

0F0FFFH

0F0000H

Number of Sectors

255

240

Number of 64 Kbyte

Blocks

MODE 3

SCK

CE#

MODE 3

DON'T CARE

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MODE 0

High-Impedance

MSb

SST25WF080B Datasheet(PDF) 5 Page - Microchip Technology

SST25WF080B Datasheet(HTML) 5 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Descarga

Enlace URL