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ST7LITE49M Datasheet(PDF) 97 Page - STMicroelectronics

No. de pieza ST7LITE49M
Descripción Electrónicos  8-bit MCU with single voltage Flash memory data EEPROM, ADC, 8/12-bit timers, and I²C interface
PDF  188 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST7LITE49M Datasheet(HTML) 97 Page - STMicroelectronics

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ST7LITE49M
On-chip peripherals
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Autoreload register (ATR1L)
Reset value: 0000 0000 (00h)
Bits 11:0 = ATR1[11:0] Autoreload register 1:
This is a 12-bit register which is written by software. The ATR1 register value is
automatically loaded into the upcounter CNTR1 when an overflow occurs. The register
value is used to set the PWM frequency.
PWM Output Control register (PWMCR)
Reset value: 0000 0000 (00h)
Bits 7:0 = OE[3:0] PWMx output enable bits
These bits are set and cleared by software and cleared by hardware after a reset.
0: PWM mode disabled. PWMx Output Alternate function disabled (I/O pin free for
general purpose I/O)
1: PWM mode enabled
PWMX Control Status register (PWMxCSR)
Reset value: 0000 0000 (00h)
Bits 7:4= Reserved, must be kept cleared.
Bit 3 = OP_EN One Pulse Mode Enable bit
This bit is read/write by software and cleared by hardware after a reset. This bit enables
the One Pulse feature for PWM2 and PWM3 (only available for PWM3CSR)
0: One Pulse mode disable for PWM2/3.
1: One Pulse mode enable for PWM2/3.
Bit 2 = OPEDGE One Pulse Edge Selection bit
This bit is read/write by software and cleared by hardware after a reset. This bit selects
the polarity of the LTIC signal for One Pulse feature. This bit will be effective only if
OP_EN bit is set (only available for PWM3CSR)
0: Falling edge of LTIC is selected.
1: Rising edge of LTIC is selected.
7
0
ATR7
ATR6
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
Read/write
7
0
0OE30OE2
0OE10OE0
Read/write
7
0
0000
OP_EN
OPEDGE
OPx
CMPFx
Read/write



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