AX88796ALF datasheet(21/68 Pages) ASIX

21 / 68 page

AX88796ALF

3-in-1 Local Bus Fast Ethernet Controller

4.0 Basic Operation

4.1 Receiver Filtering

The address filtering logic compares the Destination Address Field (first 6 bytes of the received packet) to the Physical

address registers stored in the Address Register Array. If any one of the six bytes does not match the pre-programmed

physical address, the Protocol Control Logic rejects the packet. This is for unicast address filtering. All multicast

destination addresses are filtered using a hashing algorithm. (See following description.) If the multicast address indexes a

bit that has been set in the filter bit array of the Multicast Address Register Array the packet is accepted, otherwise the

Protocol Control Logic rejects it. Each destination address is also checked for all 1’s, which is the reserved broadcast

address.

4.1.1 Unicast Address Match Filter

The physical address registers are used to compare the destination address of incoming packets for rejecting or accepting

packets. Comparisons are performed on a byte wide basis. The bit assignment shown below relates the sequence in

PAR0-PAR5 to the bit sequence of the received packet.

PAR0

DA7

DA6

DA5

DA4

DA3

DA2

DA1

DA0

PAR1

DA15

DA14

DA13

DA12

DA11

DA10

DA9

DA8

PAR2

DA23

DA22

DA21

DA20

DA19

DA18

DA17

DA16

PAR3

DA31

DA30

DA29

DA28

DA27

DA26

DA25

DA24

PAR4

DA39

DA38

DA37

DA36

DA35

DA34

DA33

DA32

PAR5

DA47

DA46

DA45

DA44

DA43

DA42

DA41

DA40

Note: The bit sequence of the received packet is DA0, DA1, … DA7, DA8 ….

AX88796ALF Datasheet(PDF) 21 Page - ASIX Electronics Corporation

AX88796ALF Datasheet(HTML) 21 Page - ASIX Electronics Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

Datasheet Descarga

Enlace URL