AX88796ALF datasheet(38/68 Pages) ASIX

38 / 68 page

AX88796ALF

3-in-1 Local Bus Fast Ethernet Controller

5.1.3 Interrupt mask register (IMR) Offset 0FH (Write)

FIELD

NAME

DESCRIPTION

Reserved

RDCE

DMA Complete Interrupt Enable. Default “low” disabled.

CNTE

Counter Overflow Interrupt Enable. Default “low” disabled.

OVWE Overwrite Interrupt Enable. Default “low” disabled.

TXEE

Transmit Error Interrupt Enable. Default “low” disabled.

RXEE

Receive Error Interrupt Enable. Default “low” disabled.

PTXE

Packet Transmitted Interrupt Enable. Default “low” disabled.

PRXE

Packet Received Interrupt Enable. Default “low” disabled.

5.1.4 Data Configuration Register (DCR) Offset 0EH (Write)

FIELD

NAME

DESCRIPTION

Reserved

6:2

Reserved

WTS

Word Transfer Select

0: Selects byte-wide DMA transfers.

1: Selects word-wide DMA transfers.

5.1.5 Transmit Configuration Register (TCR) Offset 0DH (Write)

FIELD

NAME

DESCRIPTION

FDU

Full Duplex:

This bit indicates the current media mode is Full Duplex or not. Ignore this setting when

using internal PHY. MAC duplex will be control by internal PHY duplex status.

0: Half duplex

1: Full duplex

Pad Disable

0: Pad will be added when packet length less than 60.

1: Pad will not be added when packet length less than 60.

RLO

Retry of late collision

0: Don’t retransmit packet when late collision happens.

1: Retransmit packet when late collision happens.

4:3

Reserved

2:1

LB1, LB0 Encoded Loop-back Control

These encoded configuration bits set the type of loop-back that is to be performed.

LB1 LB0

Mode 0

Normal operation

Mode 1

Internal AX88796A loop-back

Mode 2

PHYcevisor loop-back

CRC

Inhibit CRC

0: CRC appended by transmitter.

1: CRC inhibited by transmitter.

AX88796ALF Datasheet(PDF) 38 Page - ASIX Electronics Corporation

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