WM8804 datasheet(24/66 Pages) WOLFSON

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WM8804

Production Data

PD Rev 4.1 September 2007

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

PLL4

06h

PRESCALE

PLL Pre-scale Divider Select

0 = Divide by 1 (PLL input clock =

oscillator clock)

1 = Divide by 2 (PLL input clock =

oscillator clock

÷ 2)

PLL5

07h

1:0

FREQMODE[1:0]

PLL Post-scale Divider Select

Selects the PLL output divider value

in conjunction with MCLKDIV and

CLKOUTDIV.

Refer to Table 23 for details of

FREQMODE operation.

Note: FREQMODE[1:0] bits are

automatically set in S/PDIF

Receive Mode.

Table 22 Pre and Post PLL Clock Divider Control

PLL CONFIGURATION EXAMPLE

Consider the situation where the oscillator clock (OSCCLK) input frequency is fixed at 12MHz and

the required MCLK frequency is 12.288MHz.

Calculate the f2, FREQMODE and MCLKDIV Values

The PLL is designed to operate with best performance when the f2 clock is between 90 and 100MHz.

The necessary MCLK frequency is 12.288MHz. Choose MCLKDIV and FREQMODE values to set

the f2 frequency in the range of 90 to 100MHz. In this case, the default values (MCLKDIV = 0 and

FREQMODE[1:0] = 10) will set the f2 frequency at 98.304MHz; this value is within the 90 to 100MHz

range and is hence acceptable.

•

MCLKDIV = 0

•

FREQMODE[1:0] = 10

•

f2 = 98.304MHz

Calculate R Value

Using the relationship: R = (f2 ÷ f1), the value of R can be calculated.

•

R = (f2 ÷ f1)

•

R = (98.304 ÷ 12)

•

R = 8.192

Calculate PLL_N Value

The value of PLL_N is the integer (whole number) value of R, ignoring all digits to the right of the

decimal point. In this case, R is 8.192, hence PLL_N is 8.

Calculate PLL_K Value

The PLL_K value is simply the integer value of (222 (R-PLL_N)).

•

PLL_K = integer part of (222 x (8.192 – 8))

•

PLL_K = integer part of 805306.368

•

PLL_K = 805306 (decimal) / C49BA (hex)

A number of example configurations are shown in Table 23. Many other configurations are possible;

Table 23 shows only a small number of valid possibilities.

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