Motor de Búsqueda de Datasheet de Componentes Electrónicos
  Mexican  ▼
ALLDATASHEET.COM.MX

X  

Preview PDF HTML

CSG14K_CSG8K Datasheet(PDF) 98 Page - OSRAM GmbH

No. de pieza CSG14K_CSG8K
Descripción Electrónicos  13.8 Mp_8.3 Mp High Speed Global Shutter CMOS Image Sensor
PDF  114 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrónico  OSRAM [OSRAM GmbH]
Página de inicio  http://www.osram.com
Logo OSRAM - OSRAM GmbH

CSG14K_CSG8K Datasheet(HTML) 98 Page - OSRAM GmbH

Back Button CSG14K_CSG8K Datasheet HTML 94Page - OSRAM GmbH CSG14K_CSG8K Datasheet HTML 95Page - OSRAM GmbH CSG14K_CSG8K Datasheet HTML 96Page - OSRAM GmbH CSG14K_CSG8K Datasheet HTML 97Page - OSRAM GmbH CSG14K_CSG8K Datasheet HTML 98Page - OSRAM GmbH CSG14K_CSG8K Datasheet HTML 99Page - OSRAM GmbH CSG14K_CSG8K Datasheet HTML 100Page - OSRAM GmbH CSG14K_CSG8K Datasheet HTML 101Page - OSRAM GmbH CSG14K_CSG8K Datasheet HTML 102Page - OSRAM GmbH Next Button
Zoom Inzoom in Zoom Outzoom out
 98 / 114 page
background image
Document Feedback
CSG14K_CSG8K
Functional Description
Datasheet
• PUBLIC
DS000571
• v2-01 • 2023-Feb-10
113
│ 97
The status bits can be enabled on the CTRL channel or observed on one of the digital test
output pins.
Attention
Enabling the not-safe-to-request status bits on the CTRL channel might influence the control word in
idle state. It is therefore recommended to perform control channel training with EN_NSF set to ‘0’.
7.8.4
Digital Test Output
Figure 124:
Digital Test Output Register
Reg. Name
Bank
Addr
Bits
Description
DMUX1_SEL
3
50-51
[9:5]
Sets pin TDIG1 function
DMUX2_SEL
3
50-51
[14:10]
Sets pin TDIG2 function
A number of digital signals of the chip can be monitored in real-time during normal sensor
operation via the sensor output pins TDIG1 to TDIG4. This can be useful for testing and
debugging the system without having to rely on the sub-LVDS implementation of the control
channel, so a test pad or connection to the FPGA is recommended.
Selecting which signal to be monitored is done with DMUX1_SEL registers for TDIG1
(bottom) and TDIG3 (top) and with DMUX2_SEL registers for TDIG2 (bottom) and TDIG4
(top).
Figure 125:
TDIG Mapping
DMUX*_SEL
Description
0
PLL lock status
8
Global sampling phase(1)
9
Exposure status (group S)
10
Exposure status (group L)
11
EOBVAL
12
SVAL
13
FVAL
14
DVAL
24
NSRF (Not-Safe-to request frame status bit)
25
NSRE (Not-Safe-to request exposure status bit)
(1)
GLOB time seen on TDIG pin is only a fraction of the real GLOB time. GLOB program still extends after
falling edge of this signal.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Descarga

Go To PDF Page


Enlace URL



¿ALLDATASHEET es útil para Ud.?  [ DONATE ] 

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Enlace a la hoja de datos    |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com