Bottom PoP Technologies

Amkor’s popular Package Stackable Very Thin Fine Pitch BGA (PSvfBGA)

platform supports single die, stacked die using wirebond or hybrid (FC

plus wirebond) stacks and has been applied to Flip Chip (FC) applications

to improve warpage control and package integrity through test and SMT

handling.

As handheld microprocessors have transitioned to advanced CMOS nodes

with higher speed cores with higher I/O, there has been a transition from

wirebond to flip chip die designs. Flip chip enables the use of an exposed

die bottom package that integrates the package stacking design features

of PSvfBGA in a fcCSP assembly flow, which Amkor calls Package Stackable

Flip Chip Chip Scale Package (PSfcCSP). PSfcCSP has a thin exposed FC die

enabling fine pitch stacked interfaces at 0.5 mm pitch which is a challenge

in a center molded PSvfBGA structure.

Continued development resulted in Amkor entering the second generation

of PoP applications where new memory architectures, required in mobile

multimedia applications, demand higher density stacked interfaces in

combination with PoP mounted area and height reductions. The previous

PSvfBGA and PSfcCSP structures limited the ability of the memory interface to

scale in density and pitch, resulting in the need for a new bottom PoP structure.

Amkor developed new technologies to create the next-generation PoP

solution with interconnect vias through the mold cap. Known as Through

Mold Via (TMV®), this technology provides a stable bottom package that

enables use of thinner substrates with a larger die to package ratio. TMV®

enabled PoP can support single, stacked die or FC designs. TMV® is an ideal

solution for the emerging 0.4 mm pitch low power DDR2 memory interface

requirements and enables the stacked interface to scale with solder ball

pitch densities to 0.3 mm pitch or below.

The next few years promise to provide many new challenges and

applications for PoP, as handheld multimedia applications continue to

demand higher signal processing power and data storage capabilities.

Amkor is committed to maintaining strong development and production

capabilities to ensure we are at the forefront in meeting next-generation

PoP requirements.

Applications

PoP packages are designed for products requiring efficient memory

architectures including multiple buses and increased memory density and

performance, while reducing mounted area. Portable electronic products

such as mobile phones (baseband or applications processor plus combo

memory), digital cameras (image processor plus memory), portable media

players (audio/graphics processor plus memory), gaming and other mobile

applications can benefit from the combination of stacked package and

small footprint offered by Amkor’s PoP family.

Package-on-Package (PoP)

TECHNOLOGY SOLUTIONS

BENEFITS AS AN ENABLING

TECHNOLOGY

PoP offers OEMs and EMS providers

a flexible platform to cost effectively

integrate logic plus memory devices in

a 3D stacked architecture. Integration

through PoP provides technical and

business/logistics benefits.

f

Greatly expands device and supplier

options by simplifying the business

logistics of stacking

f

Integration controlled at the

system level to best match stacked

combinations including memory

architecture with the system

requirements

f

JEDEC standards ensure broad

component availability

f

Improving time-to-market, inventory

management and supply chain

flexibility

f

Eliminates margin stacking and

expands technology reuse

f

Provides the lowest total cost of

ownership where complex 3D

integration of logic plus memory is

required