HT86R384 datasheet(13/41 Pages) HOLTEK

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HT86R384

Rev. 0.10

May 18, 2007

Preliminary

As an interrupt is serviced, a control transfer occurs by

pushing the Program Counter onto the stack and then

branching to subroutines at the specified location(s) in

the program memory. Only the Program Counter is

pushed onto the stack. The programmer must save the

contents of the register or status register (STATUS) in

advance if they are altered by an interrupt service pro-

gram which corrupts the desired control sequence.

External interrupt is triggered by a high-to-low/

low-to-high transition of INT pin which sets the related

interrupt request flag (EIF:bit 4 of INTC). When the inter-

rupt is enabled, and the stack is not full and the external

interrupt is active, a subroutine call to location 04H will

occur. The interrupt request flag (EIF) and EMI bits will

be cleared to disable other interrupts.

The internal Timer/Event Counter 0 interrupt is initial-

ized by setting the Timer/Event Counter 0 interrupt re-

quest flag (T0F:bit 5 of INTC), caused by a Timer/Event

Counter 0 overflow. When the interrupt is enabled, and

the stack is not full and the T0F bit is set, a subroutine

call to location 08H will occur. The related interrupt re-

quest flag (T0F) will be reset and the EMI bit cleared to

disable further interrupts.

The internal Timer/Event Counter 1 interrupt is initial-

ized by setting the Timer/Event Counter 1 interrupt re-

quest flag (T1F:bit 6 of INTC), caused by a Timer/Event

Counter 1 overflow. When the interrupt is enabled, and

the stack is not full and the T1F bit is set, a subroutine

call to location 0CH will occur. The related interrupt re-

quest flag (T1F) will be reset and the EMI bit cleared to

disable further interrupts.

The internal Timer Counter 2 interrupt is initialized by

setting the Timer Counter 2 interrupt request flag

(T2F:bit 0 of INTCH), caused by a Timer Counter 2 over-

flow. When the interrupt is enabled, and the stack is not

full and the T2F bit is set, a subroutine call to location

10H will occur. The related interrupt request flag (T2F)

will be reset and the EMI bit cleared to disable further in-

terrupts.

The internal Timer Counter 3 interrupt is initialized by

setting the Timer Counter 3 interrupt request flag

(T3F:bit 1 of INTCH), caused by a Timer Counter 3 over-

flow. When the interrupt is enabled, and the stack is not

full and the T3F bit is set, a subroutine call to location

14H will occur. The related interrupt request flag (T3F)

will be reset and the EMI bit cleared to disable further in-

terrupts.

During the execution of an interrupt subroutine, other in-

terrupt acknowledges are held until the RETI instruction

is executed or the EMI bit and the related interrupt con-

trol bit are set to 1 (of course, if the stack is not full). To

return from the interrupt subroutine, the RET or RETI in-

struction may be invoked. RETI will set the EMI bit to en-

able an interrupt service, but RET will not.

Interrupts occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In the case of simultaneous requests,

the following table shows the priority that is applied.

These can be masked by resetting the EMI bit.

The Timer/Event Counter 0/1 interrupt request flag

(T0F/T1F) which enables Timer/Event Counter 0/1 con-

trol bit (ET0I/ET1I), the Timer Counter 2/3 interrupt re-

quest flag (T2F/T3F) which enables Timer Counter 2/3

control bit (ET2I/ET3I), and external interrupt request

flag (EIF) which enables external interrupt control bit

(EEI) form the interrupt control register (INTC:0BH and

INTCH:1EH). EMI, EEI, ET0I, ET1I, ET2I, and ET3I are

used to control the enabling/disabling of interrupts.

These bits prevent the requested interrupt begin ser-

viced. Once the interrupt request flags (T0F, T1F, T2F,

T3F, EIF) are set, they will remain in the INTC/INTCH

software instruction.

It is recommended that application programs do not use

²CALL² subroutines within an interrupt subroutine. Inter-

rupts often occur in an unpredictable manner or need to

be serviced immediately in some applications. If only

one stack is left and the interrupt enable is not well con-

trolled, once a

²CALL² subroutine if used in the interrupt

subroutine will corrupt the original control sequence.

Interrupt Source

Priority

Vector

External Interrupt

04H

Timer/Event Counter 0 Overflow

08H

Timer/Event Counter 1 Overflow

0CH

Timer Counter 2 Overflow

10H

Timer Counter 3 Overflow

14H

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