TMP88CU74F datasheet(9/132 Pages) TOSHIBA

9 / 132 page

TMP88CU74

2003-02-17

88CU74-9

Figure 1.4.2 Examples of Resonator Connection

Note:

Accurate Adjustment of the Oscillation Frequency

Although no hardware to externally and directly monitor the basic clock pulse is not provided, the

oscillation frequency can be adjusted by making the program to output fixed frequency pulse to the

port with disabling all interrupts and watchdog timers, and monitoring this pulse. With a system

requiring adjustment of the oscillation frequency, the adjusting program must be created

beforehand.

1.4.2

Timing Generator

The timing generator generates the various system clocks supplied to the CPU core and

peripheral hardware from the basic clock (fc or fs). The timing generator provides the

following functions.

Generation of main system clock (fm)

Generation of divider output ( DVO ) pulses

Generation of source clocks for time base timer

Generation of source clocks for watchdog timer

Generation of internal source clocks for timer/counters TC1-TC6

Generation of internal clocks for serial interfaces SIO and HSO

Generation of source clocks for VFT driver circuit

Generation of warm-up clocks for releasing STOP mode

Generation of a clock for releasing reset output

(1) Configuration of timing generator

The timing generator consists of a 3-stage prescaler, a 21-stage divider, a main

system clock generator, and machine cycle counters.

The clock fc/4 or fc/8, that is output from the 2nd stage or the 3rd stage of the

prescaler, can be selected as the clock to input to the 1st stage of the divider by DV1CK

(bit 5 in CGCR). Inputting fc/8 to the 1st stage of the divider operates the peripheral

circuit without the setting change when the operation clock is multiplied by 2.

(Example: 8 MHz to 12.5 MHz)

The DV1CK should be set the peripheral circuit prior to starting the peripheral

circuits. Do not change the set value after setting.

An input clock to the 7th stage of the divider depends on the operating mode, DV1CK

(bit 5 in DVCR), and DV7CK(bit 4 in TBTCR), that is shown in Table 1.4.1. As reset

and STOP mode started/canceled, The prescaler and the divider are cleared to “0”.

(a) Crystal/Ceramic resonator

(b) External oscillator

(d) External oscillator

High-frequency clock

Low-frequency clock

XIN

XOUT

XIN

XOUT

(Open)

XTIN

XTOUT

XTIN

XTOUT

(Open)

2007-10-19

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