TMP86FS49AIUG datasheet(38/296 Pages) TOSHIBA

No. de pieza	TMP86FS49AIUG

Descripción Electrónicos	8 Bit Microcontroller

PDF	296 Pages

Scroll/Zoom	100%

Fabricante Electrónico	TOSHIBA [Toshiba Semiconductor]

Página de inicio	http://www.semicon.toshiba.co.jp/eng

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Page 22

2. Operational Description

2.2 System Clock Controller

TMP86FS49AIUG

2.2.4.2

IDLE1/2 mode and SLEEP1/2 mode

IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable

interrupts. The following status is maintained during these modes.

1. Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to

operate.

2. The data memory, CPU registers, program status word and port output latches are all held in the

status in effect before these modes were entered.

3. The program counter holds the address 2 ahead of the instruction which starts these modes.

Figure 2-10 IDLE1/2 and SLEEP1/2 Modes

Reset

Reset input

“0”

“1” (Interrupt release mode)

Yes

CPU and WDT are halted

Interrupt request

IMF

Interrupt processing

Normal

release mode

Yes

Starting IDLE1/2 and

SLEEP1/2 modes by

instruction

Execution of the instruc-

tion which follows the

IDLE1/2 and SLEEP1/2

modes start instruction

TMP86FS49AIUG Datasheet(PDF) 38 Page - Toshiba Semiconductor