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TMP86FS49AIUG Datasheet(PDF) 61 Page - Toshiba Semiconductor |
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TMP86FS49AIUG Datasheet(HTML) 61 Page - Toshiba Semiconductor |
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61 / 296 page ![]() Page 45 TMP86FS49AIUG 4. Special Function Register (SFR) The TMP86FS49AIUG adopts the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function register (SFR) or the data buffer register (DBR). The SFR is mapped on address 0000H to 003FH, DBR is mapped on address 0F80H to 0FFFH. This chapter shows the arrangement of the special function register (SFR) and data buffer register (DBR) for TMP86FS49AIUG. 4.1 SFR Address Read Write 0000H P0DR 0001H P1DR 0002H P2DR 0003H P3DR 0004H P4DR 0005H P5DR 0006H P6DR 0007H P7DR 0008H P0OUTCR 0009H P1CR 000AH P4OUTCR 000BH P0PRD - 000CH P2PRD - 000DH P3PRD - 000EH P4PRD - 000FH P5PRD - 0010H TC1DRAL 0011H TC1DRAH 0012H TC1DRBL 0013H TC1DRBH 0014H TTREG3 0015H TTREG4 0016H TTREG5 0017H TTREG6 0018H PWREG3 0019H PWREG4 001AH PWREG5 001BH PWREG6 001CH ADCCR1 001DH ADCCR2 001EH ADCDR2 - 001FH ADCDR1 - 0020H SIO1CR 0021H SIO1SR - 0022H SIO1RDB SIO1TDB 0023H TC2CR 0024H TC2DRL 0025H TC2DRH |
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