AP8012H

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Fig 3. Feedback circuit

6. Leading Edge Blanking (LEB)

At the instant the internal Sense FET is turned on, there usually exists a high current spike through the Sense FET,

caused by the primary side capacitance and secondary side rectifier diode reverse recovery. Excessive voltage

across the sense resistor would lead to false feedback operation in the current mode PWM control. To counter this

effect, the device employs a leading edge blanking (LEB) circuit. This circuit inhibits the PWM comparator for a

short time (typically 350ns) after the Sense FET is turned on.

7. Under Voltage Lock Out

Once fault condition occurs, switching is terminated and the Sense FET remains off. This causes VDD to fall. When

VDD reaches the VDD reset voltage, 6V, the protection is reset and the internal high voltage current source charges

the VDD capacitor. When VDD reaches the UVLO start voltage, 14.5V, the device resumes its normal operation. In

this manner, the auto-restart can alternately enable and disable the switching of the power Sense FET until the fault

condition is eliminated.

8. Thermal Shutdown (TSD)

The Sense FET and the control IC are integrated in the same chip, making it easier for the control IC to detect the

temperature of the Sense FET. When the temperature exceeds approximately 170°C, thermal shutdown is activated,

the device turn off the Sense FET. The device will go back to work when the lower threshold temperature about

140°C is reached.