LAN9252VSLASHML datasheet(50/329 Pages) MICROCHIP

No. de pieza	LAN9252V/ML

Descripción Electrónicos	2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs

PDF	329 Pages

Scroll/Zoom	100%

Fabricante Electrónico	MICROCHIP [Microchip Technology]

Página de inicio	http://www.microchip.com

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50 / 329 page

LAN9252

DS00001909A-page 50

 2015 Microchip Technology Inc.

6.4

Device Ready Operation

The device supports a Ready status register bit that indicates to the Host software when the device is fully ready for

operation. This bit may be read via the Power Management Control Register (PMT_CTRL) or the Hardware Configura-

tion Register (HW_CFG).

Following power-up reset, RST# reset, EtherCAT chip level reset or digital reset (see Section 6.2, "Resets"), the Device

Ready (READY) bit indicates that the device has read, and is configured from, the contents of the EEPROM.

An EtherCAT reset via the Reset Control Register (RESET_CTL) will cause the EtherCAT core to reload from the

EEPROM, temporarily causing the Device Ready (READY) to be low.

Entry into any power savings state (see Section 6.3.4, "Chip Level Power Management") other than D0 will cause

Device Ready (READY) to be low. Upon wake-up, the Device Ready (READY) bit will go high once the device is

returned to power savings state D0 and the PLL has re-stabilized.

LAN9252V/ML Datasheet(PDF) 50 Page - Microchip Technology