STM32H523VCK7TR datasheet(48/228 Pages) STMICROELECTRONICS

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Functional overview

STM32H523xx

48/228

DS14540 Rev 1

3.33

Inter-integrated circuit interface (I2C)

The device embeds three I2C. Refer to Table 7 for the implemented features.

The I2C bus interface handles communications between the microcontroller and the serial

I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.

The I2C peripheral supports:

•

I2C-bus specification and user manual rev. 5 compatibility:

–

Slave and Master modes, multimaster capability

–

Standard-mode (Sm), with a bit rate up to 100 Kbit/s

–

Fast-mode (Fm), with a bit rate up to 400 Kbit/s

–

Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s and 20 mA output drive I/Os

–

7- and 10-bit addressing modes, multiple 7-bit slave addresses

–

Programmable setup and hold times

–

Optional clock stretching

•

System management bus (SMBus) specification rev 3.0 compatibility:

–

Hardware PEC (packet error checking) generation and verification with ACK

control

–

Address resolution protocol (ARP) support

–

SMBus alert

•

Power system management protocol (PMBus) specification rev 1.3 compatibility

•

Independent clock: a choice of independent clock sources allowing the I2C

commun.ication speed to be independent from the PCLK reprogramming

•

Wake-up from Stop capability

•

Programmable analog and digital noise filters

•

1-byte buffer with DMA capability

Table 7. I2C implementation

I2C features(1)

1. X: supported

I2C1

I2C2

I2C3

Standard-mode (up to 100 Kbit/s)

Fast-mode (up to 400 Kbit/s)

Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)

Programmable analog and digital noise filters

SMBus/PMBus hardware support

Independent clock

Wakeup capability

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