STM32H523VCK7TR datasheet(8/228 Pages) STMICROELECTRONICS

8 / 228 page

List of tables

STM32H523xx

8/228

DS14540 Rev 1

List of tables

Table 1.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2.

STM32H523xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 3.

STM32H523 boot mode when TrustZone is disabled (TZEN = 0xC3) . . . . . . . . . . . . . . . . 23

Table 4.

STM32H523 boot mode when TrustZone is enabled (TZEN = 0xB4) . . . . . . . . . . . . . . . . 24

Table 5.

ADC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 6.

Timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 7.

I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 8.

I3C peripheral controller/target features versus MIPI v1.1 . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 9.

USART, UART and LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 10.

SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 11.

SDMMC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 12.

Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 13.

STM32H523xx pin/ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 14.

Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 15.

Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 16.

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 17.

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 18.

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 19.

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 20.

Maximum allowed clock frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 21.

Supply voltage and maximum frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 22.

Operating conditions at power-up/down (regulator ON) . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 23.

Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 24.

Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 25.

Internal reference voltage calibration value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 26.

Typical and maximum current consumption in Run mode, code with data processing

running from flash memory, 2-way instruction cache ON, PREFETCH ON . . . . . . . . . . . 104

Table 27.

Typical and maximum current consumption in Run mode, code with data processing

running from flash memory, 1-way instruction cache ON, PREFETCH ON . . . . . . . . . . . 105

Table 28.

Typical and maximum current consumption in Run mode, code with data processing

running from SRAM with cache 1-way . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 29.

Typical and maximum current consumption in Run mode, code with data processing

running from SRAM with cache 2-way . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 30.

Typical consumption in Run mode with CoreMark running

from flash memory and SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 31.

Typical consumption in Run mode with SecureMark running from

flash memory and SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 32.

Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . 108

Table 33.

Typical and maximum current consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 34.

Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . 109

Table 35.

Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 109

Table 36.

Peripheral current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 37.

Low-power mode wake-up timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 38.

High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 39.

Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 40.

4-50 MHz HSE oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 41.

Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 42.

HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

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