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Input Clock

Analog

Input

Signal

Sample

N

N + 1

N + 2

N + 3

N + 4

N + 1 4

N + 1 6

N + 1 7

N + 1 5

N − 17

N − 16

N − 15

N − 14

N − 13

N − 3

N − 2

N − 1

N

tsu

th

tSTART

tA

tEND

tPDI

Data Out

(D0−D10)

17.5 Clock Cycles

Data Invalid

Output Clock

RESET TIMING CHARACTERISTICS

RESET (Pin 35)

t1 . 10 ms

t2 . 2 ms

t3 . 2 ms

SEN Active

Power Supply

(AVDD, DRVDD)

ADS5510

SLAS499 – JANUARY 2007

A.

It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above

timing matches closely with the specified values.

Figure 1. Timing Diagram

Typical values given at T

A = 25°C, min and max specified over the full recommended operating temperature range, AVDD =

DRV

DD = 3.3 V, and 3-VPP differential clock, unless otherwise noted

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNIT

Switching Specification

t1

Power-on delay

Delay from power-on of AVDD and

10

ms

DRVDD to RESET pulse active

t2

Reset pulse width

Pulse width of active RESET signal

2

µs

t3

Register write delay

Delay from RESET disable to SEN

2

µs

active

Delay from power-up of AVDD and

Power-up time

40

ms

DRVDD to output stable

Figure 2. Reset Timing Diagram

7

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